1. Digital Integrated Circuits A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
Designing Sequential Logic Circuits
Revised from Digital Integrated Circuits, © Jan M. Rabaey el

2. Sequential Logic 2 storage mechanisms • positive feedback
• charge-based

3. Naming Conventions In our text:
a latch is level sensitive
a register is edge-triggered
There are many different naming conventions
For instance, many books call edge-triggered elements flip-flops
This leads to confusion however

4. Memory elements
At high level , memory is classified as background memory and foreground memory.
Memory that is embedded into logic is foreground memory.
Large amounts of centralized memory core is background memory, which achieves higher area density through efficient use of array structures.
Here, we focus on foreground memory elements.

5. Latch versus Register Latch Register stores data when clock is high
stores data when clock rises or falls D Q D Q
Clk
Clk
Clk
Clk D D Q Q

6. Latches

7. Latch-Based Design P latch is transparent when f = 1
N latch is transparent when f = 0 f N P
Logic
Latch
Latch
Logic

8. Timing Definitions
CLK t
Register t t D Q su
hold D
DATA
CLK
STABLE t t c 2 q Q
DATA
STABLE t
Tsetup: setup time is the time that data input D must be valid before clock transition
Thold: hold time is the time that data input D must remain valid after the clock edge
Tc2q: propagation delay of copying D to Q output (with respect to clk)

9. Characterizing Timing
Register
Latch

10. Maximum Clock Frequency
tc2q + tp,comb + tsetup <= T
Clock period T must accommodate the longest possible delay
Also another constraint: tcdreg + tcdlogic > =thold
tcd: contamination delay = minimum delay
This constraint ensures the input data of the sequential circuits is held long enough after the clock edge and not modified too soon by the new coming-in data

11. Positive Feedback: Bi-Stability1 A C B o 2 = o1
Vi2
When the gain of inverter in transient region is larger than 1, A & B are the only stable operating points, C is metastable.

12. Meta-Stability Gain should be larger than 1 in the transition region
Hence, cross coupling of two inverters results in a bistable circuit, that is a circuit with two stable states. The circuit serves as a memory, storing either a 1 or 0 (A or B)

13. Bistable circuit
In absence of triggering, a bistable circuit remains in a single state (static memory as long as power is on). Another common name for a bistable circuit is flip-flop
A FF is only useful when there is a mean to bring it from one state to the other one.
Two approaches can achieve that:
cutting the feedback loop, once the feedback loop is open, a new value can be written. This is called multiplexer based.
Overpowering the feedback loop, by applying a trigger signal at the input of the FF, a new value is forced into the circuit by overpowering the previous stored value.

14. Mux-Based Latches Negative latch Positive latch
(transparent when CLK= 0)
Positive latch
(transparent when CLK= 1)
CLK 1 D Q 1 D Q
CLK

15. Mux-based Static Latch
The most robust and common technique to build a latch is
to use transmission-gate multiplexers.
Use the clock as a decoupling signal, that distinguishes
between the transparent and opaque states
Clock load is 4, clock activity
factor is 1, so more power

16. Mux-Based Latch
Clock load reduced to 2 at the cost of static power consumption
NMOS only
Non-overlapping clocks

17. Static Latch: an alternativeD
CLK I1 T1 I2
Eliminating the feedback, we can obtain another implementation of a latch by cross-coupling the inverters. In this case, the transmission gate and source driver D must overpower the feedback to switch the state.
So now sizing is important. If minimum-sized devices are used in transmission gates, it is essential that transistors of inverter I2 be made even weaker.

18. Master-Slave (Edge-Triggered) Register
The most common approach for constructing an edge-triggered
Register is to use a master-slave configuration, which consists
of cascading a (negative/positive) latch with a
(positive/negative) one.

19. Master-Slave Register design
At low phase of the clock, master stage is transparent and D is passed to QM. (During this time, slave stage is in hold mode, keeping its value using feedback).
On the rising edge, master stage stops sampling and slave starts sampling.
At high phase of the clock, slave samples output QM, while master is in hold mode. Since QM is constant now, Q makes one transition per clock cycle. The value of Q is the value of D right before the rising edge.

20. Clk-Q Delay
Tsetup

21. Setup Time
Voltage at input of T2

22. Timing properties of Master-Slave Register (first order estimation)
Assume inverters have the same delay Tinv and transmission gates have the same delay Ttp
Setup time:
Propagation time:
Hold time:
2Tinv + Ttp
Ttp + 2Tinv

23. Reduced Clock Load Master-Slave Register
Reverse conduction
When I4 is a weak device, it is not a major problem
Does this problem appear in the previous register?

24. Avoiding Clock Overlap
Direct path from D to Q
CLK
CLK Q A X D B
Driving the same node
CLK
CLK
(a) Schematic diagram
CLK
CLK
(b) Overlapping clock pairs
Problem at 0-0 overlap?

25. Avoiding Clock Overlap
When clock goes high, master stage should stop sampling the input and go into hold mode. Since CLK and CLK are both high for a short period of time, there is a direct path from D to Q. As a result, Q might change during the overlap period, which is undesired for edge-trigger registers. This is known as a race condition in which Q is a function of whether D arrives at node X before or after the falling edge of the CLK.
Also, if there is clock overlap between CLK and CLK, node A can be driven by both D and B, which may result in an undefined state.
These problems can be avoided by using two non-overlapping clocks.

26. 2 phase non-overlapping clocks
Note: During non-overlap time, both latches are in high-impedance state (feedback loop is open, gain is 0). So, this duration should not be long.

27. Overpowering the Feedback Loop ─ Cross-Coupled Pairs
NOR-based set-reset
Cross-coupled NANDs
What if they need to be clocked?

28. Ratioed CMOS SR latch Added clock
This is not used in datapaths any more, but is a basic building memory cell

29. Output voltage dependence on transistor width
Sizing Issues
Output voltage dependence on transistor width
Transient response
Boundary condition: current equal

30. Storage Mechanisms Static latch Dynamic (charge-based) latch
CLK D Q
CLK
A stored value remains valid as long as power supply is applied.
Drawback: complexity
Temporary storage of charge on parasitic capacitors, similar to dynamic logic. Periodic refresh may be necessary.

31. Dynamic transmission gate register
CLK
CLK A B D
Q=D
CLK
CLK
This implementation is very efficient since it requires only 8 transistors (6 if NMOS only switches). The reduced transistor count is attractive for high-performance data path.
Setup time:
Propagation time:
Hold time:
Ttp
Ttp + 2Tinv

32. Correct operation of dynamic register
CLK
CLK D Q
CLK
CLK
Positive-edge triggered register
Since registers are periodically clocked, the storage nodes are constantly updated.
Clock overlap might be an important concern. During 0-0 overlap period, a direct path for data flow from D to Q exists (a race condition occurs). The same is true for 1-1 overlap period.
0-0 overlap can be addressed if there is enough delay between D input and Q. 1-1 overlap can be taken care of by enforcing that the hold time larger than the overlap duration.

33. Correct operation of dynamic register
CLK
CLK D Q
CLK
CLK
Positive-edge triggered register
CLK
CLK
Hold time constraint
Ensure enough delay

34. 2-phase dynamic register

35. Making a Dynamic Latch Pseudo-Static
Dynamic register is very appealing from perspectives of complexity, performance and power consumption. But robustness limit its use. The storage node is prone to coupling, noise and leakage.
Fortunately, most of the problems can be adequately addressed by adding a weak feedback inverter and making it pseudostatic (at slight cost of delay).

36. More Precise Setup Time

37. Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)

38. Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)

39. Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)

40. Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)

41. Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)

42. Setup/Hold Time Illustrations
Hold-1 case

43. Setup/Hold Time Illustrations
Hold-1 case

44. Setup/Hold Time Illustrations
Hold-1 case

45. Setup/Hold Time Illustrations
Hold-1 case

46. Setup/Hold Time Illustrations
Hold-1 case

47. Other Latches/Registers: C2MOS
Clock overlap insensitive register: embed clock signal in the inverter
“Keepers” can be added to make circuit pseudo-static

48. Insensitive to Clock-OverlapDD DD DD DD M M M M 2 6 2 6 M M 4 8 X X D Q D Q 1 M 1 M 3 7 M M M M 1 5 1 5
(a) Equivalent circuit in (0-0) overlap
(b) Equivalent circuit (1-1) overlap
No direct path from D to Q
X can make only 0->1 transition, but can not make it to Q
CLK
CLK
Overlapping clock pairs

49. C2MOS
The circuit is insensitive to clock overlaps since overlaps activate either the pull-up or the pull-down network in master/slave stage (never both)
One potential problem is slow rise and fall of the clocks, where both NMOS and PMOS are on. This could create a path between input and output that can destroy the state.
Timing (delay) characteristics may be improved compared to transmission-gate-based static register.
CLK
CLK