1. Review for Exam 3 LC3 control State Graphs
Completeness and conflict issues
Creating transition tables and next state equations
from state graphs
Sequence detectors
One-hot encoding
Cascaded counters
UART
Asynchronous inputs

2. LC3-The Fetch Cycle MAR PC MDR Memory[MAR] PC  PC+1 IR  MDR Fetch0
enaPC
ldMAR
selMDR = 1
ldMDR
selPC=00
ldPC
Fetch1
Fetch2
enaMDR
ldIR

5. Counters and Other Finite State Machines
For counters, the state encodings are usually significant
0000
1001
0001
1000 Q0
0010 7
Segment
Decoder Q1 Q2
0111
0011 Q3
0110
0100
0101

6. For general purpose FSMs, the encoding of
the states is usually not significant
For example, in the following state graph, the
Encodings of the state are irrelevant
Event 2
Event 1 …
Event 1
Event 2
Event 3

7. State Graphs for Counters with Inputs
The INC signal determines
whether or not to transition to the next state

8. Completeness Issues This state graph is not complete. Why not?
What happens in state ’10’ when INC’ occurs?

9. Completeness Issues In order for a state graph to be complete:
It must completely specify the FSM
Paths leaving a state must specify all POSSIBLE cases
To check for completeness, OR together all of the exiting paths.
If the result is “1” then the design is complete.

10. Conflict Issues This state graph is not conflict free. Why not?
What happens in state ’10’ when CLR and INC occur simultaneously?

11. Conflict Issues In order for a state graph to be conflict free:
It must completely specify the FSM
For a given set of input conditions, the transition
from a state must be unique
To check for conflicts, AND together all pairs of the exiting paths. If the result is “0” for all pairs, the design has no conflicting transitions.

12. Creating transition tables and next state equations from state graphs

14. The resulting next state and output equations are: N1 = Q0 + Q1 TDONE’
N0 = TOKEN Q1’ Q0’
CLRT = Q0
SPRAY = Q1

15. This is a sequence detector. It has 1 input – ‘Xin’.
It detects the sequence on the input.
When detected, the output signal ‘Z’ is asserted.

16. As long as ‘Xin’ is a ‘1’ we stay in state S0.

17. When we detect a ‘0’ we move to state S1.

18. As long as ‘Xin’ is a ‘0’ we stay in state S1.

19. When we detect a ‘1’ we move to state S2.

20. If the next value of ‘Xin’ is a ‘1’ we move to state S3.
We have found
the sequence
so we also
assert the output
‘Z’.
We are done!

21. But what if the next value of ‘Xin’ is a ‘0’?
We move back to
state S1 to wait
for the next ‘1’.

22. Problems This machine is only useful for detecting the 1st
occurrence of the pattern After that, it
simply loops at state S3 forever while asserting
the ‘Z’ output.

23. Here is a modified version
It detects an occurrence
of the pattern, asserts
the output ‘Z’ for one
clock cycle and then goes
on to look for the next
occurrence of the pattern
Note: when transitioning
from state S3, a ‘0’ sends
the machine to state S1
while a ‘1’ sends it to state
S0.

24. A Mealy Version of the Detector
The major difference
is that the output ‘Z’
is asserted on the
transition ‘Xin’ from
state S2.
It is a Mealy machine
because the output is a
function of the current
state and the input.

25. A Mealy machine often allows a reduction in the
number of states necessary to implement a machine.
Here is a machine which does the same function.

26. One-Hot Encoding One-Hot encoding has the following characteristics:
There is one flip flop for each state
Only one state bit can be high at a time
One state bit must always be high
It uses more flip flops than dense encodings
Tradeoff is that input forming logic and output forming logic are usually much smaller and simpler.

27. Take for example the following state graph
b’c
b’c’ b A B C

28. State Encoding and Structure
D Q A+ A
With one-hot encoding, each state has its own flip flop.
Note: ‘A’ is the name of a state. It is also the name of the wire coming out from the flip flop for state ‘A’.
The same holds true for states ‘B’ and ‘C’
D Q B B+
D Q C C+

29. One Hot Encodings IFL and OFL can usually be created via inspection
Each state bit can be done separately from the others
Lots of don’t cares lead to simple solutions a’
By inspection we can see: A
b’c a C b B
b’c’

30. One Hot Encodings IFL and OFL can usually be created via inspection
Each state bit can be done separately from the others
Lots of don’t cares lead to simple solutions a’
By inspection we can see:
A+ = a’A + b’cB + C A
b’c a C b B
b’c’

31. One Hot Encodings IFL and OFL can usually be created via inspection
Each state bit can be done separately from the others
Lots of don’t cares lead to simple solutions a’
By inspection we can see:
A+ = a’A + b’cB + C
B+ = aA + b’c’B A
b’c a C b B
b’c’

32. One Hot Encodings IFL and OFL can usually be created via inspection
Each state bit can be done separately from the others
Lots of don’t cares lead to simple solutions a’
By inspection we can see:
A+ = a’A + b’cB + C
B+ = aA + b’c’B
C+ = bB A
b’c a C b B
b’c’

33. Cascaded Counters

34. Mod4 Counter Mod4 Counter clk Digit1 1 2 Digit0 2 3 1 2
Sequence should be: … … but we get: … …
?????
DO NOT TIE CLK inputs on modules to anything but the clock !!!!!!
Even if you tinker until you get the right count sequence, you must guarantee that signal Rollover0 has no hazards
Digit0 transition from 1-2 makes this difficult if not impossible
clk1 2
clk 2
Mod4 Counter
CLR
Mod4 Counter
CLR
INC=‘1’
‘1’
Rollover1
Rollover0
clk
Digit1 1 2
Digit0 2 3 1 2
Clk1 (Rollover0)

35. Another Common Ripple Counter
Sequence is:
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
So what is the problem? Q3 Q2 Q1 Q0
‘1’
T Q Q’
‘1’
T Q Q’
‘1’
T Q Q’
‘1’
T Q Q’
CLK

36. Timing Diagram clk Q0 changes in response to clock edge
Only after it changes does Q1’s FF get a clock
Only after that does Q2’s FF get a clock
Net effect is that all the FF’s change at different times
Logic depending on Q3 has very little time to react before next clock edge Q0 Q1 Q2 Q3

37. Do Not Use Asynchronous or Ripple Counters
Mod4 Counter 2
INC=‘1’
Rollover0
Digit0
CLR
Rollover1
Digit1
clk1
clk
‘1’
CLK
T Q Q’
‘1’ Q3 Q2 Q1 Q0

38. A Mod4 Counter The right way! Count Value D Q Clr Terminal Count IFL
Inc
Roll
Over

39. A Dataflow MUX – Version 1
module mux21(q, sel, a, b);
input sel, a, b;
output q;
assign q = (~sel & a) | (sel & b); ]
endmodule
Much simpler, less typing, familiar C-like syntax.
Synthesizer turns it into optimized gate-level design.

40. A Dataflow MUX – Version 2
module mux21(q, sel, a, b);
input sel, a, b;
output q;
assign q = sel?b:a;
endmodule
Even simpler, uses C-like ?: construct

41. A Dataflow MUX – Multi-Bit
module mux21(q, sel, a, b);
input sel;
input[15:0] a, b;
output[15:0] q;
assign q = sel?b:a;
endmodule
2:1 Mux a 16 q 16 b 16 1
sel
Same assignment statement works for multi-bit wires as for 1-bit wires.
Key Ideas: The predicate must evaluate to true or false (1 or 0) The parts getting assigned must be proper widths.

42. A Dataflow MUX – Multi-Bit
module mux21(q, sel, a, b, c, d);
input sel;
input[15:0] a, b;
output[15:0] q;
assign q = (sel==0)?a:
(sel==1)?b:
(sel==2)?c:d;
endmodule 16 a b
sel q 01 00 c d 11 10
4:1
Mux 2

43. UART Character Transmission
Line idling
Start bit
Parity bit
Stop bit
Mark
Space
Line idling again
7 data bits
The letter ‘W’ ( )
Mark 1 1 1 1 1
Space
Parity bit (odd parity)
7 data bits – Least significant bit first

44. UART Character Reception
Start bit says a character is coming
Receiver should sample in middle of bits
Mark
Space
Receiver can use a timer (counter) to time when it samples

45. UART Character Reception
If receiver samples too quickly, see what happens…
Mark
Space

46. UART Character Reception
If receiver samples too slowly, see what happens…
Mark
Space
Receiver resynchronizes every time a new start bit arrives.
Only has to be accurate enough to receive 8-9 bits

47. UART Receiving
Receiver checks to see if stop bit is there when it expects at end of character
If not, reports framing error to host CPU
New start bit can appear immediately after stop bit
Receiver will re-synchronize on start bit

48. Transmitter Block Diagram
300Hz
300 HZ
Counter
EnableCounter
Send
Transmitter
State
Machine
Count=10
Mod 10
Counter
Increment
Busy
Shift
Parity
Generator
Shift
Register
ParitySelect
Load
Dout
ParityBit
Din 7

49. Transmitter FSM A one-hot state encoding
Send’
Reset/Load, Shift
Idle
Send
Load
Load, Busy, ResetCounter, ResetBRG
Send’
A one-hot state encoding
would make for a simple implementation.
Be sure to choose state encodings and use hazard-free logic minimization that ensures Busy signal will have no hazards…
Wait
Send
Busy
Count
300Hz’
300Hz
Count=10
Shift
Count=10’
Shift, Increment, Busy

50. Asynchronous Signals
Problem: asynchronous signals do not respect setup and hold times
Signals may change at any time ok ok
bad
bad ok ok
Tsu Th
Clock

51. Metastability
Imagine if R pulsed high for a very short time and back low
Could it impart enough energy to get Q halfway between ‘1’ and ‘0’? Yes.
Latch might hang in the midway point for some time
Called metastability
S=0
R=0
Q=1
Q’=0

52. Metastability
Violating tsetup for a D flip flop can cause very short pulses on signals Y and Z, and make flip flop metastable D Y Q Q’ Z
CLK

53. Solution #1: Synchronize Signal A
IFL
IFL now sees
synchronous
input
5ns N1
D Q C1
D Q A
clk
10ns N0
D Q C0
clk
clk
Synchronizing flip flop still susceptible to going metastable due to setup time violations. Solution beyond scope of this class.

54. Solution #2: Use Gray Codes for States
Will never have case when both paths transitioning… 11 A A’ 00 01 A A’ 00
IFL
5ns N1
D Q C1 A
clk
10ns N0
D Q C0
clk
State change will occur or it won’t…

55. Solution #2 – Doesn’t Always Work
To understand the problem, need to understand hazards.

56. Gates Have Real Timing…F g1 A’
B=1 F A
C=1 g2
Called a false output – static equations indicate F=1 but dynamic behavior gives a “glitch”

57. Solution #3
Use both gray code states and hazard-free logic minimization
Gray codes ensure only one state bit changes
HFLM ensures no hazards (false outputs) exist 11 S 01 S’
D Q
IFL A N0 N1 C0 C1
5ns
10ns
clk