1. Latches, Flip-Flops BIL- 223 Logic Circuit Design Ege University Department of Computer Engineering

2. A TV channel control example CH 2 CH 3 CH 1 0 0 1 1 1 0

3. Introduction to Sequential Circuits Combinational Logic Storage Elements Inputs Outputs State Next State  Sequential circuits Combinational logic circuits State information (stored in memory)  Output is a function of inputs and present state  Can be synchronous or asynchronous clock

4. Clocks and synchronization  A clock is a special device that whose output continuously alternates between 0 and 1.  The time it takes the clock to change from 1 to 0 and back to 1 is called the clock period, or clock cycle time.  The clock frequency is the inverse of the clock period. The unit of measurement for frequency is the hertz.  Clocks are often used to synchronize circuits.  They generate a repeating, predictable pattern of 0s and 1s that can trigger certain events in a circuit.  If several circuits share a common clock signal, they can coordinate their actions with respect to one another.  This is similar to how humans use real clocks for synchronization. clock period

5. 0.4 0.5 0.4 S Y 0.2 Storing Information 0.2 ns 0.5 ns0.4 ns

6. SR Latch SRQQNQN 00QQ 0101 1010 1100 Reset Set Undefined No Change S Q QNQNQNQN R S R Q QNQNQNQN Race, and Unstable S R SR

7. SR Latch SRQQNQN 0011 0110 1001 11QQ R Q QNQNQNQN S Reset Set Undefined No Change SR S R

8. SR Latch with Control Input CSRQQNQN 0XXQQ 100QQ 10101 11010 11111 Q QNQNQNQN R C S Reset Set Undefined No Change

9. D LatchQ QNQNQNQN C D CDQQNQN 0XQQ 1001 1110 D with 1 Control D C D C D with 0 Control

10. Transparency  D Latch is called “transparent”: Output follows input instantaneously  Desired behavior: Y changes only once per clock pulse C D QQ

11. Latch Transparency Problem C 1 DQD

12. C S R Q Q C R Q Q C S R Q S Q S-R Master-Slave Flip-Flop Y C S R Y Q Glitch 1s Catching Problem Master Slave S and R must be stable during clock pulse for the correct operation PULSE TRIGGERED

13. Negative Edge Triggered D Flip-Flop C Q2 D C S R Q Q C Q Q C D Q D Q Q1Q1Q1Q1

14. Positive Edge Triggered D Flip-Flop C S R Q Q C Q Q C D Q D Q C Q1 D Q2

15.  Pulse Triggered  Edge-Triggered: Triggered D (b) Master-Slave Flip-Flops D C Triggered D Triggered SR S R C D C S R C (c) Edge-Triggered Flip-Flops Triggered D D C D C Standard Symbols for Flip-Flops

16. Direct Inputs  Direct R and/or S inputs that control the state of the latches within the flip-flops asynchroniously.  For the example flip-flop shown  0 applied to R resets the flip-flop to the 0 state  0 applied to S sets the flip-flop to the 1 state D C S R Q Q

17. S-R Flip-Flop Descriptors 0 0 1 1 OperationS 0 1 0 1 R No change Reset Set Undefined 0 1 ? Q(t+1) Q(t) Operation No change Set Reset No change S X 0 1 0 Q(t+ 1) 0 1 1 0 Q(t) 0 0 1 1 R X 0 1 0 Characteristic TableExcitation Table Characteristic Equation

18. D Flip-Flop Descriptors Characteristic TableExcitation Table Characteristic Equation D 0 1 Operation Reset Set 0 1 Q(t1) + Q(t+1) 0 1 0 1 D Operation Reset Set

19. J-K Flip-flop D C K J J C K 0 0 1 1 No change Set Reset Complement OperationJ 0 1 0 1 K 0 1 Q(t +1) Q(t) Q(t) Q(t + 1) 0 1 1 0 Q(t) 0 0 1 1 Operation X X 0 1 K 0 1 X X J No change Set Reset No Change Characteristic TableExcitation Table Characteristic Equation

20. T Flip-flop Characteristic TableExcitation Table Characteristic Equation C D T T C No change Complement Operation 0 1 TQ(t1) Q(t) Q(t) + Q(t + 1) Q(t) 1 0 T No change Complement Operation Q(t)

21. Flip-flop Behavior Example  Use the characteristic tables to find the output waveforms for the flip-flops shown: T C Clock D,T QDQD QTQT D C

22. Flip-Flop Behavior Example (continued)  Use the characteristic tables to find the output waveforms for the flip-flops shown: J C K S C R Clock S,J QSR QJK R,K ?