1. Latches and Flip-Flops ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning

2. 311_112 Set-Reset Latch S R Q' Q

3. 311_113 Set-Reset Latch S R Q' Q 0 0 1 0 0 1

4. 311_114 Set-Reset Latch S R Q' Q 0 0 1 0 0 1 / 1 / 0 / 1 / 0/ 1

5. 311_115 0 / 1 / 0 0 / 1/ 0 Set-Reset Latch S R Q' Q 1 0 0 1/ 0 / 1

6. Switch Debouncing 6

7. D Latch 311_117

8. Edge-Triggered D Flip-Flop 311_118

9. Timing Parameters 311_119

10. J-K and T Flip-Flops 311_1110

11. J-K FF Timing Diagram 311_1111

12. T FF Timing Diagram 311_1112 (Falling-Edge Triggered)

13. Additional Inputs 311_1113

14. Sequential Circuits 311_1114

15. Summary  Latches S-R (Set-Reset) D (Data)  Flip-Flops (Edge-Triggered) D (Data) J-K (Set-Reset-Toggle) T (Toggle) 311_1115