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Sequential Logic. Logic Styles Combinational circuits – Output determined solely by inputs – Can draw solely with left-to-right signal paths.

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Presentation on theme: "Sequential Logic. Logic Styles Combinational circuits – Output determined solely by inputs – Can draw solely with left-to-right signal paths."— Presentation transcript:

1 Sequential Logic

2 Logic Styles Combinational circuits – Output determined solely by inputs – Can draw solely with left-to-right signal paths

3 Logic Styles Sequential circuits – Output determined by inputs AND previous outputs – Feedback loop

4 AB Circuit If A = 1 output must be 1 ABO 00 01 101 111

5 AB Circuit If A = 0 and B = 1 output must be 0 ABO 00 010 101 111

6 AB Circuit If A = 0 and B = 0 output may be 1 or 0 ABO 000/1?? 010 101 111

7 AB Circuit Need to consider hidden input: ABLast Out Out 0000 0011 01x0 10x1 11x1

8 AB Circuit Describe next output O t+1 in terms of current output O t ABO t+1 00OtOt 010 101 111

9 Clocks Crystal Oscillators – Vibrate at known frequency when current applied – Used to generate clock signal:

10 Logisim Clock Clock alternates between high and low Button makes a nice manual clock

11 Hertz Frequency inverse of cycle time – Expressed in hertz. 1 Hz = 1 cycle per second 1 kilohertz (kHz) 1000 cycles/sec 1 megahertz (MHz) 1 million cycles/sec 1 gigahertz (GHz) 1 billion cycles/sec

12 Clocks Timing can be – Level-triggered : change can happen when clock high – Edge-triggered : change can happen on edge

13 Latches Latch : Level triggered memory

14 Flip Flops Flip Flop : edge triggered memory – Logisim won't reproduce

15 SR Circuit Set Reset circuit SRQ t+1 00QtQt 010 101 11 undefined

16 Logisim To simulate SR need to add noise to delays

17 Logisim Oscillation : Circuit trapped in flip/flop – need to restart

18 Clocked SR Latch Level triggered based SR circuit SRQ t+1 00QtQt 010 101 11 undefined

19 Clocked JK Latch JK makes SR safe – Prevent 1/1 from getting to SR - flips SRQ t+1 00QtQt 010 101 11

20 D Latch D Latch : Stores single bit during low clock DQ t+1 00 11

21 Memory's Atom Basic building block of memory

22 Logisim Built in D Flipflop – D – Clock – Preset (force 1) – Clear (force 0) – Enable (1 or floating is on)

23 Registers Register : Array of D Flip-flops

24 Registers Register : Write requires clock and write signal

25 Main Memory Big old matrix of flip flops

26 Main Memory 2-4 decoder logic picks memory address

27 Main Memory 3 bits wide

28 Implemeneted


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