1. StateCAD FPGA Design Workshop

2. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to:  Describe how to add states and transitions to a state diagram design  List the four wizards available in StateCAD  Access the Configuration GUI to change compiler options

3. For Academic Use Only Presentation Name 3 Outline  Overview  Beginning a Diagram  States and Transitions  Wizards  Compilation  Summary

4. For Academic Use Only Presentation Name 4 StateCAD Translates state diagrams to HDL based designs Automatically analyzes designs for problems such as – Stuck-at states – Conflicting state assignments – Indeterminate conditions Includes StateBench

5. For Academic Use Only Presentation Name 5 StateCAD  Support concurrent state machines  Graphical operators for states  Mealy & Moore outputs  Resets  Combinatorial and synchronous logic  Text comments

6. For Academic Use Only Presentation Name 6 FSM Wizard in StateCAD

7. For Academic Use Only Presentation Name 7 Logic Wizard in StateCAD  StateCAD Logic Wizard for data flow structures – Shifters, registers,latches, counters, muxes, etc.  Requires object type, attributes, and signal names  Handles boolean equations within the wizard

8. For Academic Use Only Presentation Name 8 Overview  StateCAD diagrams have.dia extensions – File names have an eight character limit  StateCAD output – Language specific files VHDL, Verilog, or ABEL VHDL and Verilog output files can be compiled using various tools – Exemplar – Synopsys

9. For Academic Use Only Presentation Name 9 Outline  Overview  Beginning a Diagram  States and Transitions  Wizards  Compilation  Summary

10. For Academic Use Only Presentation Name 10 Beginning a Diagram Project  New Source State Diagram File Name

11. For Academic Use Only Presentation Name 11 Outline  Overview  Beginning a Diagram  States and Transitions  Wizards  Compilation  Summary

12. For Academic Use Only Presentation Name 12 Adding States  In the Draw Mode tool bar, use the State Mode command  States are given unique names when they are added or copied – May be used as actual state names – Can be changed or edited  Syntax of states: NAME_ONLY NAME OUTPUTS=1;

13. For Academic Use Only Presentation Name 13 Outputs Output list contains equations – Output equations – State variables Outputs support complex data flow logic – Bit or vector equations – Counters – Muxes Example: NAME CNTR <= CNTR + 1; BUSOUT = (sigA OR sigB) AND NOT(sigC OR sigD)

14. For Academic Use Only Presentation Name 14 Outputs  Output Wizard is the easiest way to add outputs – In Edit State (double-click on a state), select the Output Wizard button

15. For Academic Use Only Presentation Name 15 Transitions Use the Transition button to draw curved and straight transitions: – Straight transitions: Click on one state, then click on another state – Curved transitions: Click on one state (a small square appears), another small square will follow the cursor (click to place), one more square will appear, place the final square on the state destination

16. For Academic Use Only Presentation Name 16 Curved Transitions Multiple segment transitions – Enable through Options menu  Graphics – Deselect “Single Segment Curve” Unlimited number of segments Each segment contains a starting point, two control points, and an endpoint

17. For Academic Use Only Presentation Name 17 Transition Conditions To add a transition condition, double-click on the transition for the Edit Condition dialog box Conditions are Boolean equations – Syntax errors and indeterminate conditions are checked during compilation Conditions may use inputs, outputs, and logic variables – State names and variables from one machine may be used in the condition of another machine. This allows communication between state machines

18. For Academic Use Only Presentation Name 18 Reset  Reset is taken from any state, when its condition is true  One synchronous and one asynchronous reset are allowed per state machine  Reset condition should not contain variables used in any other transition of the state machine – Reset overrides the state transition conditions

19. For Academic Use Only Presentation Name 19 Reset  Use the Reset Mode command:  Click on an empty region for your start point  Click on the desired reset state  You will automatically be asked to select the mode (asynchronous or synchronous)  The condition is automatically added (Reset)

20. For Academic Use Only Presentation Name 20 Text and Comments  To add text and comments to state diagrams, use the Text Mode: Enter text here Add as comments to HDL code Make attributes visible

21. For Academic Use Only Presentation Name 21 Text and Comments  Test vectors added into the HDL and included files can be referenced by including text in HDL  Language specific logic not supported by StateCAD may be implemented  Caution: When adding comments in HDL, text lines may be broken by StateCAD, and the new line will begin without a comment marker in HDL

22. For Academic Use Only Presentation Name 22 Outline Overview Beginning a Diagram States and Transitions Wizards Compilation Summary

23. For Academic Use Only Presentation Name 23 Wizards  FSM Wizard or – Allows you to quickly create basic state machines  Optimization Wizard or – Collects information on design goals and target devices, to provide optimized results for speed, area, gate count, etc. – Optimizes code for target device AND synthesis tool  Design Wizard – Combines FSM Wizard and Optimization Wizard into one – Only available through the Wizard Toolbar (Window  Wizard Toolbar)

24. For Academic Use Only Presentation Name 24 Wizards Logic Wizard or – Develops data flow logic – Supports counters, muxes, shifters, latches, and gates Wizard Toolbar

25. For Academic Use Only Presentation Name 25 Outline Overview Beginning a Diagram States and Transitions Wizards Compilation Summary

26. For Academic Use Only Presentation Name 26 Compilation  Compilation translates state diagrams into HDL – Automatic error checking, logic minimization, state assignments – Performs syntax check, language problems, and design problems

27. For Academic Use Only Presentation Name 27 Compiler Configuration Options Access Configurations options through the menu bar: – Options  Configuration Options – Delete unread variables – Retain output values – Implied else Language

28. For Academic Use Only Presentation Name 28 Compiler Configuration Options Check options – Indeterminate transitions – Conflicting State assignments State Assignments

29. For Academic Use Only Presentation Name 29 Outline Overview Beginning a Diagram States and Transitions Wizards Compilation Summary

30. For Academic Use Only Presentation Name 30 Summary  State diagrams can be translated into VHDL, Verilog, or ABEL  Numerous toolbars are available to aid in your diagram design  States and state transitions are easily added through buttons in the Draw Mode Toolbar  The Output Wizard gives access to the Logic Wizard, so you can easily add output equations or conditions to any state or transition  Designs are compiled and translated with a simple push button

31. For Academic Use Only Presentation Name 31 Outline Overview Beginning a Diagram States and Transitions Wizards Compilation Summary