1. © Copyright Xilinx 2004 All Rights Reserved 9 November, 2004 XUP Virtex-II Pro Development System

2. © Copyright Xilinx 2004 All Rights Reserved XUP Virtex-II Pro Development System 2 Agenda Virtex-II Pro: Curriculum-on-a-Chip Designed for Education Features Availability Software Donations

3. © Copyright Xilinx 2004 All Rights Reserved XUP Virtex-II Pro Development System 3 Curriculum-on-a-Chip Virtex-II Pro XC2VP30 FPGA 30,816 Logic Cells 2448 Kbits of BRAM 2 PowerPC 405 processors 8 MultiGigabit Serial Transceivers 8 Digital Clock Management blocks 136 18x18 multipliers A powerful, versatile, low-cost development system for education

4. © Copyright Xilinx 2004 All Rights Reserved XUP Virtex-II Pro Development System 4 Virtex-II Pro Development System Powerful: Virtex-II Pro XC2VP30 FPGA – 30,816 Logic Cells, 2 PowerPC 405 processors, 8 multi gigabit transceivers (4 available on board), 2448 Kbits of Block RAM, 136 18x18 multipliers Versatile – Teaching and research – Digital design, computer architecture, operating systems, networking, embedded systems, digital signal processing, image & video processing, digital communications, and more Low-cost … US$299 per board from www.digilentinc.com – With donation of 4 on-board Xilinx devices

5. © Copyright Xilinx 2004 All Rights Reserved XUP Virtex-II Pro Development System 5 Designed with Education in Mind Special startup mode for extensive self-test – Eliminates doubts about board integrity I/O Expansion and Protection – High and low-speed I/O connectors – Under and over voltage protection on low speed I/O – Range of low-cost expansion boards from Digilent inc USB Configuration mode – Fast, low-cost download Compact Flash storage – Individual project backup Power supply current measurement

6. © Copyright Xilinx 2004 All Rights Reserved XUP Virtex-II Pro Development System 6 Designed with Education in Mind Compact Flash card interface for individual project back-up or IBM Miicrodrives with upto 8Gbit capacity USB port for FPGA Configuration using standard USB cable Support for supply current monitoring Self-test / configuration Flash memory I/O under and over voltage protection

7. © Copyright Xilinx 2004 All Rights Reserved XUP Virtex-II Pro Development System 7 Memory Hierarchy Virtex-II Pro XC2VP30 FPGA 2448 Kbits of BRAM 30,816 Logic Cells (Distributed RAM) Expandable memory up to 2 Gigabytes DDR SDRAM DIMM Slot Non-volatile Platform Flash PROM for configuration storage Compact Flash card interface for individual project back-up or IBM Microdrives with up to 8Gbit capacity

8. © Copyright Xilinx 2004 All Rights Reserved XUP Virtex-II Pro Development System 8 System Expansion Additional I/O via user supplied four 60-pin headers High-speed connectors compatible with Digilent module boards High-speed Gigabit serial I/O User Supplied SMA Low-speed connectors compatible with Digilent peripheral boards High-speed Gigabit serial I/O Serial ATA connectors Virtex-II Pro XC2VP30 FPGA 4 of 8 Rocket I/O Tranceivers (MGTs) 120 max of 556 User I/O

9. © Copyright Xilinx 2004 All Rights Reserved XUP Virtex-II Pro Development System 9 Digital I/O 4 Digital Breadboard Digilent Low cost, low speed plug-in modules to expand the curriculum High speed plug-in modules coming soon: video module in Jan 2005 Visit www.digilentinc.com Digilent System Expansion Modules 1W Amplified Speaker Digital I/O 5512K SRAM and Flash 1MHz Analog Acquisition

10. © Copyright Xilinx 2004 All Rights Reserved XUP Virtex-II Pro Development System 10 General Features Video via XSGA connector 10/100 Ethernet PHY + Connector Buttons, Switches, and LEDs Audio via AC97 codec and standard connectors Keyboard and mouse 2 PS-2 Ports RS-232

11. © Copyright Xilinx 2004 All Rights Reserved XUP Virtex-II Pro Development System 11 Clocks, Power & Reset Power Switch and 5V input On-board switching power supplies (1.5V, 2.5V, 3.3V) May be disabled for application of external power Support for current measurement On board clock oscillators 100 MHz system clock 32 MHz for system ACE 75 MHz serial ATA (on back) User Supplied Clock RELOAD/RESET Reloads configuration data from CompactFlash or PlatformFlash Processor reset External Clock for MGTs (user supplied alternate) External clock via high-speed connector Virtex-II Pro XC2VP30 FPGA 8 Digital Clock Management (DCM) blocks Power requirements of 1.5V, 2.5V, 3.3V

12. © Copyright Xilinx 2004 All Rights Reserved XUP Virtex-II Pro Development System 12 Block Diagram 2VP30 Compact Flash Configuration DDR SDRAM DIMM USB Configuration AC97 Audio CODEC & Stereo AMP 75 MHz SATA clock 10/100 Ethernet PHY Three Serial ATA connectors RS232 PS-2 (x2) Buttons (5), LEDs (4), switches (4) Platform Flash Configuration High-speed and low-speed I/O expansion connectors SVGA Additional I/O via four user- supplied 60-pin headers Internal Power Supplies 3.3V, 2.5V, and 1.5V External Power 100 MHz system clock 2 user supplied clocks One 3.125 Gbps port via 4 user-supplied SMA connectors

13. © Copyright Xilinx 2004 All Rights Reserved XUP Virtex-II Pro Development System 13 Virtex-II Pro Development System Availability Available in quantity from Jan 2005 Purchase from Digilent – US$299 per board from www.digilentinc.com With donation of 4 on-board Xilinx devices Donations from Xilinx – See XUP donation request form at www.xilinx.com/univ

14. © Copyright Xilinx 2004 All Rights Reserved XUP Virtex-II Pro Development System 14 Software Donations Universities have access to all Xilinx Software – Professors can install software on any machine in the University (site license) – On-line donation form at www.xilinx.com/univ