1. Ch.8 Layout Verification TAIST ICTES Program VLSI Design Methodology Hiroaki Kunieda Tokyo Institute of Technology

2. 8.1 DRC/LVS

3. Layout Design Gate Level Simulatior Layout Design Netlist Mask Data Layout Netlist DRC/LVS Functional Verification ATPG Test Pattern

4. DRC & LVS [Objective] to check design rule violation by DRC CAD (Design Rule Checker) and to check validity of layout by LVS CAD (Layout versus Schematic). [Method] 1. DRC uses computational geometry to check relation of overlap or distance between polygons of either the same or the different layers. 2. LVS uses schematic derived from layout result to compare components and connections between original schematic and derive one. [Problem] 1. Reduction of scan path flip flops 2. Speed up of testing such as concurrent testing

5. L ａｙｏｕｔ Design 4 DRC (Design Rule Checker)

6. Problems when wire are too wide or narrow. Polysilicon should extend beyond boundary of difusion area. The cut of via must connect elements and not mistakenly connect to substrate or others. Design Rule

7. Metal1 min-width=3λ, min-sep= 3λ Metal2 min-width=3λ, min-sep= 3λ poly min-width=2λ, min-sep= 2λ n, p-dif min-width=3λ, min-sep(n-n, p-p)=3λ (n-p10λ) Tube min-width=10λ, min-distance(tub-active)= 5λ Transistors min-W/L=3λ/2λ poly extension= 2λ dif extension= 2λ active-poly/metal via=λ min-sep(tran.-tran.)= 2λ min-sep(tran-tub.tie) = 3λ SCMOS Design Rules

8. Vias cuts=2λx2λ via =4λx4λ n,p.diff-poly, poly-metal1 n,p.diff-metal1, metal1-metal2 Tub ties cuts =2λx2λ metal =4λx4λ Metal1 min-width=6λ, min-sep= 4λ available via to metal2 Special rules cut to poly – poly sep =3λ poly.cut-dif.cut sep=2λ cut-tran.active sep =2λ dif.cut-dif sep = 4λ meta2.via must not be directly over polysilicon Prohibit small negative features. SCMOS Design Rules (continue)

9. Mask Pattern Analysis Clock wise direction for outer boundary Anti-clock wise direction for inner boundary

10. Logic Operations ORAND SuB ExOR

11. 8.2 Post Layout Simulation

12. Basic Operation of Circuit Extraction NOT, AND, OR between 2 masks grow and shrink operation over masks. 1) extraction of transistors AND(poly - p/n.diff) 2) identify via grow cut AND( grown-cut, metal, poly ) Circuit Extraction

13. Cg: gate capacitance = 0.9fF/μm 2 (2 μprocess) Cgs/Cgd: source/drain overlap capacitance =Cox W (Cox: gate/bulk overlap capacitance) Transistor Parasitics

14. C j0 = ε Si /x d = Cjo/[sqrt(1+Vr/Vbi)] Depletion region capacitance C j0 : zero-bias depletion capacitance ε Si : permittivity of silicon x d : thickness of depletion region depending on applied voltage. Wire Parasitics Junction capacitance

15. Plate capacitance per unit area assumes infinite parallel plates. A fringe capacitance per unit perimeter must be added to take into consideration of the changes in electrical field at the edges. Plate and fringe MOS capacitance

16. 0.3fF/cm 2 (overlapping area) 0.1fF/cm 2 metal 3 Depending on distance

17. Ohms per square [Ω/ ] = Sheet resistance Resistance Measurement 0.5 μm process (λ=0.25 μm) 1)Polysilicon resistance Rpoly=[18/3]x4[ Ω/ ]=24 Ω 2)n-diffusion resistance [(9/3)+(6/3)+1/2]x 2 [Ω/ ] =11 Ω

18. 8.3 Test

19. L ａｙｏｕｔ Design 5 ATPG (Test Pattern Generation) [Objective] to generate test patterns to test IC after fabrication. [Method] D algorithm is used to generate test patterns, automatically. to prove coincidence of logic functions between HDL description and logic gate circuit. [Problem] 1. Reduction of scan path flip flops 2. Speed up of testing such as concurrent testing

20. Ｌｏｇｉｃａｌ Ｆａｕｌｔ Ｍｏ ｄｅｌ 1.Stuck-at-0/1 Fault model : Logic value of wire segment is stuck at either logic 0 or logic 1. 2.Single Fault: only one fault happens for each sample. 3.Fault Test: logic circuit is tested by inserting various test input vectors and by observing its output, to check whether any single fault at each wire segment does not occur. 4.ATPG: Automatic Test Pattern Generator is a CAD software to find out necessary input test vectors. 5.Tester: in manufacture factory, tester is implemented so as to check volumes of chips in a short time, automatically.

21. Fault Difference Function Test vectors, satisfying 1. to drive 1 at wire with stuck at 0 fault 2. to set D, which is either 0 at fault or 1 at normal. 3. to transmit D to the output

22. D Algorithm 1.For stuck-at-fault 0, find out condition of inputs to set up 1. 2.Set D at the wire. 3.Decide wire logic values for D to be transmitted to output.