1. CMOS Process Flow

2. Important modules in CMOS Flow
Isolation
Wells
Gate Stack
Junctions
Interconnects
We use a variety of “unit processes” and put them together
in an appropriate sequence for CMOS “process integration”

3. Chemical Cleaning Silicon wafer must be cleaned at every step
RCA cleaning, invented in 1965, and its variants have been
the basis of almost all the cleaning procedures today
All chemicals are CMOS grade, high purity
Water used is De-Ionized (DI) Water r > 18 M-ohm cm
I. Organic clean : 5:1:1 for 10min
II. Oxide strip: 50:1 H2O:HF for 1 min
III. Ionic clean : 6:1:1 for 10min
IV. Oxide strip: 50:1 H2O:HF for 1 min
V. DI water dump rinse & dry

4. Oxidation f(Temperature, Pressure, Oxygen dilution, …)
Thermal Oxidation
T > 800oC
Si + O SiO2
Deal-Grove Model
Tox t
B and B/A are parabolic and linear rate constants
f(Temperature, Pressure, Oxygen dilution, …)

5. Ion implantation Analytical versus Monte-Carlo modeling
B, As, P, In, Sb C
(cm-3) x
User defined parameter: Species, Dose, Energy, Tilt, Rotation
Analytical: Gaussian, Skewed Gaussian, Pearson distributions
Table look-up in simulator
Monte-Carlo: Statistical simulation of random collision events
Encountered by implanted species in Silicon substrate
Computationally inefficient

6. Diffusion Solution of Diffusion Equation (Conservation of matter)
D = Diffusivity = f(Temp,Background,Interstitials,Vacancy)
Ø = Potential
C = Concentration of diffusing impurity
Simulator should have accurate model for diffusivity D

7. Deposition classification
Physical Vapour Deposition
Chemical Vapour Deposition
Sputtering
Evaporation
Mostly used for Metals
Low temperature process
but step coverage is not good
Oxide, Nitride, Poly-Silicon
LPCVD, APCVD
Plasma Enhanced (PECVD)
is attractive for low thermal budget
Excellent step coverage can be
achieved

8. LPCVD Oxide deposition
LTO:
T ~ 400oC
SiH4 + O SiO2 + H2
TEOS:
T ~ 700oC
Si(OC2H5)4 + O SiO2 + byproducts
User defined parameters: Process type, Temperature, Pressure,
Concentration of reactants…
Model requirement: Deposition rate as a function of
constituent variables

9. Nitride & Poly-Si deposition
T~ 800oC
3SiCl2H2 + 4NH Si3N4 + 6HCl + 6H2
Poly-Si:
T~ 600oC
SiH Si + H2
Model requirement:
Predict deposition thickness, step coverage, resistivity (Poly-Si)
Poly-Si resistivity can be modulated in the range ohm-cm

10. Etching classification
Wet
Dry (Plasma)
Anisotropic
Isotropic
Other constraint: Selectivity to etch stop material
User defined parameters: Type of etching, Concentration of
chemicals/gases, pressure, RF power…
Model requirement: Predict the etch rate, etch profile

11. Photolithography
Contact (1:1) and/or Projection (N:1) Printing, using UV light
through a chrome coated quartz/glass mask with opaque and
transparent region, defining features in the design
Optics for projection
Projection litho is industry standard for CMOS
Photoresist : Light sensitive organic material
Poly-Si Si

12. Photolithography Photoresist (PR) : Organic, light sensitive film
Positive PR : Weakens when exposed to UV light and then
gets etched away in developer solution
Negative PR : Hardens when exposed to UV light and then
does not etch away in developer solution
Positive PR is the industry standard for CMOS, since it
generally better well defined smaller features
UV source evolution :
1980s and early 1990s, Hg arc lamp
436 nm (g line), 365 nm (i line)
Late 1990s to present : Deep UV , excimer laser
248 nm KrF, 193 nm ArF
Resolution enhancement techniques (computational nano-litho) :
Phase shift litho (R=k1l/NA; phase of light)
Immersion litho (R=k1l/n*sina ; air vs water, n=1 vs 1.44)
Proximity correction
Sub wavelength features for assisting

13. ISOLATION MODULE SiO2 is used to isolate two transistors
LOCal Oxidation of Silicon (LOCOS)
Shallow Trench Isolation

14. LOCOS Isolation Active Litho, Dry etch Si ~15nm Si3N4 LPCVD Si
~10nm Pad SiO2
Dry oxide Si
~500nm Field SiO2
Wet oxide Si
Strip nitride, oxide
Wet etch Si Si
Scalability is an issue
due to Bird’s beak
Not suitable for < 250nm

15. Shallow Trench Isolation
Active Litho,
Dry etch
~350nm depth Si
~15nm Si3N4
LPCVD Si
~10nm Pad SiO2
Dry oxide Si Si
Liner oxide (~10nm)
HDPECVD trench fill
TEOS chemistry Si
Chemical Mechanical
Polishing, HF dip,
Nitride strip

16. Well Module

17. Requirements Adjust Vt, by SCE control Prevent Deep Punch Through Si
Account for high
fields at trench
corner
USE CHAIN OF IMPLANTS

18. Well Implant Chain P-Well N-Well
Boron ~ 200 KeV, 1012 – 1013 /cm2
Boron ~100 KeV, 1012 – 1013 /cm2
Boron ~50 KeV, 1012 – 1013 /cm2
Boron ~ 15 KeV, 1012 – 1013 /cm2
Indium ~ 120 KeV, 1012 – 1013 /cm2
Phosphorus ~ 600 KeV, 1012 – 1013 /cm2
Phosphorus ~300 KeV, 1012 – 1013 /cm2
Phosphorus ~ 50 KeV, 1012 – 1013 /cm2
Phosphorus ~ 15 KeV, 1012 – 1013 /cm2
Antimony ~ 150 KeV, 1012 – 1013 /cm2
Additional Well masks & Implants for Multiple Vt Technology

19. Gate Stack Module
SiO2, Dual Polysilicon Gate

20. Drawn channel length LD
Upsizing on reticle based on optical projection ratio
LMASK

21. Printed channel length
LMASK
Optics for projection
LPRINT
LPRINT need not be equal to LD due to optical bias

22. (Poly) Gate length LG LG need not be equal to LD due to etch bias
Typically LG < LD

23. Metallurgic channel lengthLG LM
LM < LG due to the lateral diffusion of source/drain implants

24. Effective channel lengthLG LM
Leff is electrically measured length from I-V characteristics
Leff < = LM

25. Dimension vs Pitch Scaling
Pitch scaling has become increasingly
Difficult
Dimension scaling leads pitch scaling
Definition of technology node has
become very fuzzy

26. Technology Life Cycle
Source : ITRS

27. International Technology Roadmap for Semiconductors (ITRS) trends

28. Intel’s Technology node vs minimum feature
S. Thomson et. al. , IEDM 2002 , pp

29. INTEL’s 22nm CMOS Technology
FinFET
Single FinFET
SRAM
Array
High K, Metal gate, Strained Silicon, Cu and low-k
Debate at IEDM 2012 on Intel’s claim of 22nm CMOS

30. ITRS Projections Year of Production 2013 2016 2019 2022 2025
Technology Node (nm)
(DRAM Half pitch) 28 20
14.2 10
7.1
Transistor Gate Length in Microprocessors circuits (nm)
15.3
11.7
8.9
6.6
Wafer diameter (inch) 12 18
Transistors density in Microprocessor (billion / cm2)
1.59
3.19
6.38
12.77
25.54
Number of interconnect wiring levels in the Microprocessor 13 14 15 16
Operating voltage (V)
0.85
0.77
0.71
0.64
0.59

31. The distribution across Technologies

32. Polysilicon Gate stack
i-PolySilicon
LPCVD Si
Dry, 800C, O2+N2
Nitridation Si
RCA Clean
Phase Shift Litho
Resist Trim Si
Poly Etch Si

33. Junction Module

34. NMOS Halo and Extension
Boron, 45o tilt, ~1012, 15KeV
NMOS S/D Litho Si
Arsenic, 0o tilt, ~1014, 5KeV Si

35. PMOS Halo and Extension
Phosphorus, 45o tilt, ~1012, 35KeV Si
PMOS S/D Litho Si
BF2, 0o tilt, ~1014, 3 KeV Si

36. Spacer Formation Deposit 10nm Oxide, 40nm nitride Si
Anisotropic nitride etch Si

37. Deep S/D Implant and Anneal
NMOS S/D Litho
Arsenic, 15 KeV, ~1015 Si
PMOS S/D Litho
Boron, 5 KeV, ~1015 Si Si
RTA
Trade off between poly depletion,
versus
Junction depth & Boron Penetration

38. Silicide Formation S D G Parasitic Channel Resistance PVD Metal RTA
ETCH METAL Si

39. Interconnect Module

40. ILD0 , Contact and Metal1 ILD0 CVD Contact Litho & Etch W CVD and CMPSi
ILD0 CVD
Contact Litho & Etch
W CVD and CMP
Aluminum PVD
Metal Litho & Etch
Forming gas anneal
Same process continues for Via1, Metal2, Via2, Metal3 …

41. Interconnect delay in Nano CMOS
Intrinsic gate delay
Delay
Interconnect delay
0.18
0.25
0.35
0.5
Technology node (mm)
Gate delay decreases due to decrease in gate capacitance
Interconnect delay increases due to decreasing metal line width
and increasing intra-metal coupling capacitance
Interconnects are no longer afterthought in Nano CMOS

42. Copper Interconnects Dual Damascene Process
ILD CVD (thickness for via and metal)
Litho Via holes and etch via hole
Litho Metal trenches and etch metal trench
Copper Electroplating and CMP Si