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EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 1 1 Chapter 6 Test Compression.

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Presentation on theme: "EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 1 1 Chapter 6 Test Compression."— Presentation transcript:

1 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 1 1 Chapter 6 Test Compression

2 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 2 2 What is this chapter about?  Introduce the basic concepts of test data compression  Focus on stimulus compression and response compaction techniques  Present and discuss commercial tools on test compression

3 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 3 3 Test Compression  Introduction  Test Stimulus Compression  Test Response Compaction  Industry Practices  Concluding Remarks

4 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 4 4 Introduction  Why do we need test compression?  Test data volume  Test time  Test pins  Why can we compress test data?  Deterministic test vector has “don’t care” (X’s)

5 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 5 5 (Source: Blyler, Wireless System Design, 2001) 1 2 4 8 16 32 64 0 10 20 30 40 50 60 70 Gate count (Mg) Volume of test data (Gb) Test data volume increases with circuit size Test data volume v.s. gate count

6 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 6 6 Test compression categories  Test Stimulus Compression  Code-based schemes  Linear-decompression-based schemes  Broadcast-scan-based schemes  Test Response Compaction  Space compaction  Time compaction  Mixed time and space compaction

7 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 7 7 Architecture for test compression Core Decompressor Compactor Stimulus Response Compacted Response Compressed Stimulus Low-Cost ATE

8 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 8 8 Test stimulus compression  Code-based schemes  Linear-decompression-based schemes  Broadcast-scan-based schemes

9 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 9 9 Test stimulus compression  Code-based schemes  Dictionary code (fixed-to-fixed)  Huffman code (fixed-to-variable)  Run-length code (variable-to-fixed)  Golomb code (variable-to-variable)

10 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 10 10 Code-based schemes  Dictionary code (fixed-to-fixed)

11 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 11 11 Code-based schemes  Huffman code (fixed-to-variable)

12 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 12 12 Code-based schemes  Huffman code (fixed-to-variable)

13 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 13 13 Code-based schemes  Run-length code (variable-to-fixed)

14 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 14 14 Code-based schemes  Golomb code (variable-to-variable)

15 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 15 15 Code-based schemes  Golomb code (variable-to-variable)

16 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 16 16 Test stimulus compression  Linear-decompression-based schemes  Combinational linear decompressors  Fixed-length sequential linear decompressors  Variable-length sequential linear decompressors  Combined linear and nonlinear decompressors

17 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 17 17 Linear-decompression-based schemes

18 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 18 18 Linear-decompression-based schemes

19 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 19 19 Linear-decompression-based schemes

20 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 20 20 Linear-decompression-based schemes  Combinational linear decompressors XOR Network MISR

21 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 21 21 s1 s2 s3 o1 o2 o3o4 o5 XOR network: a 3-to-5 example

22 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 22 22 Linear-decompression-based schemes  Fixed-length sequential linear decompressors

23 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 23 23 Linear-decompression-based schemes  Variable-length sequential linear decompressors  Can vary the number of free variables  Better encoding efficiency  More control logic and control information

24 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 24 24 Linear-decompression-based schemes  Combined linear and nonlinear decompressors  Specified bits tend to be highly correlated  Combine linear and nonlinear decompression together can achieve greater compression than either alone

25 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 25 25 Test stimulus compression  Broadcast-scan-based schemes  Broadcast scan  Illinois scan  Multiple-input broadcast scan  Reconfigurable broadcast scan  Virtual scan

26 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 26 26 Broadcast-scan-based schemes  Broadcast scan

27 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 27 27 Generate patterns for broadcast scan  Force ATPG tool to generate patterns for broadcast scan

28 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 28 28 Broadcast scan for a pipelined circuit  Broadcast scan for a pipelined circuit

29 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 29 29 Broadcast-scan-based schemes  Illinois scan architecture (a) Broadcast mode (b) Serial chain mode

30 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 30 30 Broadcast-scan-based schemes  Reconfigurable broadcast scan  Reduce the number of channels that are required  Static reconfiguration –The reconfiguration can only be done when a new pattern is to be applied  Dynamic reconfiguration –The configuration can be changed while scanning in a pattern

31 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 31 31 Broadcast-scan-based schemes  First configuration is: 1->{2,3,6}, 2->{7}, 3->{5,8}, 4->{1,4}  Other configuration is: 1->{1,6}, 2->{2,4}, 3->{3,5,7,8}

32 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 32 32 Broadcast-scan-based schemes  Block diagram of MUX network

33 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 33 33 Broadcast-scan-based schemes  Virtual scan  Pure MUX and XOR networks are allowed  No need to solve linear equations  Dynamic compaction can be effectively utilized during the ATPG process  Very little or no fault coverage loss

34 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 34 34 Test response compaction  Space compaction  Time compaction  Mixed time and space compaction

35 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 35 35 Test response compaction

36 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 36 36 Taxonomy of various response compaction schemes Compaction Schemes IIIIII SpaceTimeCFSCFILinearityNonlinearity Zero-aliasing Compactor [Chakrabarty 1998] [Pouya 1998]  Parity Tree [Karpovsky 1987]  Enhanced Parity Tree [Sinanoglu 2003]  X-Compact [Mitra 2004]  q-Compactor [Han 2003]  Convolutional Compactor [Rajski 2005]  OPMISR [Barnhart 2002]  Block Compactor [Wang 2003]  i-Compact [Patel 2003]  Compactor for SA [Wohl 2001]  Scalable Selector [Wohl 2004] 

37 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 37 37 Test response compaction  Space compaction  Zero-aliasing linear compaction  X-compact  X-blocking  X-masking  X-impact

38 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 38 38 Space compaction  Zero-aliasing linear compaction

39 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 39 39 An example of response graph

40 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 40 40 Space compaction  X-compact  X-tolerant response compaction technique  X-compact matrix  Error masking

41 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 41 41 Space compaction  X-compact

42 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 42 42 Space compaction  X-compactor with 8 inputs and 5 outputs

43 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 43 43 X-compact Matrix S= SC1 SC2 SC3 SC4 SC5 SC6 SC7 SC8 O= O1 O2 O3 O4 O5 M X S = O T

44 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 44 44 Space compaction  X-blocking (or X-bounding)  X’s can be blocked before reaching the response compactor  Can ensure that no X’s will be observed  May result in fault coverage loss  Add area overhead and may impact delay

45 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 45 45 Space compaction  Illustration of the x-blocking scheme

46 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 46 46 Space compaction  X-masking  X’s can be masked off right before the response compactor  Mask data is required to indicate when the masking should take place  Mask date can be compressed –Possible compression techniques are weighted pseudo- random LFSR reseeding or run-length encoding

47 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 47 47 Space compaction  An example of X-masking circuit

48 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 48 48 Space compaction  X-impact  Simply use ATPG to algorithmically handle the impact of residual x’s on the space compactor  Without adding any extra circuitry

49 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 49 49 Space compaction  Handling of X-impact

50 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 50 50 Space compaction  Handling of aliasing

51 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 51 51 Test response compaction  Time compaction  A time compactor uses sequential logic to compact test responses  MISR is most widely adopted  n-stage MISR can be described by specifying a characteristic polynomial of degree n

52 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 52 52 Multiple-input signature register (MISR)

53 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 53 53 Test response compaction  Mixed time and space compaction

54 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 54 54 Industry practices  OPMISR+  Embedded Deterministic Test  Virtual Scan and UltraScan  Adaptive Scan  ETCompression

55 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 55 55 Industry solutions categories  Linear-decompression-based schemes  Two steps –ETCompression, LogicVision –TestKompress, Mentor Graphics –SOCBIST, Synopsys  Broadcast-scan-based schemes  Single step –SPMISR+, Cadence –VirtualScan and UltraScan, SynTest –DFT MAX, Synopsys

56 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 56 56 Industry practices  OPMISR+  Cadence  Roots in IBM ‘s logic BIST and ATPG technology

57 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 57 57 General scan architecture for OPMISR+

58 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 58 58 Industry practices  Embedded Deterministic Test (TestKompress)  Mentor Graphics  First commercially available on-chip test compression product

59 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 59 59 EDT (TestKompression) architecture

60 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 60 60 TestKompress stimuli compression

61 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 61 61 TestKompress response compaction

62 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 62 62 Industry practices  Virtual Scan and UltraScan  SynTest  First commercial product based on the broadcast scan scheme using combinational logic for pattern decompression

63 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 63 63 VirtualScan architecture

64 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 64 64 UltraScan architecture

65 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 65 65 Industry practices  Adaptive Scan  Synopsys  Designed to be the next generation scan architecture

66 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 66 66 Adaptive scan architecture

67 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 67 67 Industry practices  ETCompression  LogicVision  Built upon embedded logic test (ELT) technology

68 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 68 68 ETCompression architecture

69 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 69 69 Summary of industry practices MISR: multiple-input signature register MUX: multiplexers PRPG: pseudo-random pattern generator TDDM: time-division demultiplexer TDM: time-division multiplexers XOR: exclusive-OR

70 EE141 VLSI Test Principles and Architectures Ch. 6 - Test Compression – P. 70 70  Test compression is  An effective method for reducing test data volume and test application time with relatively small cost  An effective test structure for embedded hard cores  Easy to implement and capable of producing high-quality tests  Successfully as part of design flow  Need to unify different compression architectures Concluding remarks

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