1. © 2009 Renesas Technology America, Inc. 1 Introduction  Purpose  This course provides an introduction to the R8C Family of microcontrollers (MCUs) designed and offered by Renesas Technology Corp. for cost-sensitive 8-bit embedded applications  Objectives  Review the requirements of 8-bit embedded system applications.  Understand how the R8C Family of MCUs addresses the requirements of tomorrow’s applications, and how the product line will evolve in the future.  Learn about key features and benefits these MCUs provide and how they facilitate system development.  Content  36 pages (including this page)  5 questions  Learning Time  50 minutes

2. © 2009 Renesas Technology America, Inc. 2 R8C Family in Renesas MCU/MPU Portfolio H8S (35 MHz) H8SX (50 MHz)  High Performance CISC with FPU R32C (50 MHz) 32-Bit H8 (20 MHz) RX/200 (50 MHz) RX/600 (100 MHz) SH-4A (600 MHz) RISC CISC  Application specific integration  Scalable solutions for general purpose M16C (32 MHz)  Lowest cost MCUs 16-Bit 8-Bit R8C (20 MHz)  Superscalar & MMU  Video and audio processing SH-2, SH-2A (200 MHz) 32-Bit R-Secure (20 MHz)

3. © 2009 Renesas Technology America, Inc. 3 MCU Selection Criteria  Efficient, scalable architecture  Instruction and code compatibility to move up and down within a family that offers useful choices of memory size, performance, and peripheral integration  High peripheral integration  More resources built into the chip to simplify designs, save cost  Reliable operation and EMC compliance  Extended fail-safe mechanisms  Low EMI and excellent EMS to satisfy stricter safety and environmental regulations  Efficient system development environment  Low-cost integrated development environment with comprehensive toolchain  Optimized C compiler  Efficient on-chip debug capability

4. © 2009 Renesas Technology America, Inc. 4 Top 8 Reasons To Select R8C MCUs 1. Scalable Architecture 4. Versatile 2. Powerful 3. Efficient 7. Trusted & Flexible 6. Quiet 5. Reliable  Numerous Fail-Safe Features  Integration of System Components  Rich Peripheral Set  1-wire Debugging  Robust and Secured Flash Technology  Various Reprogramming Options  16-bit CPU  Single-cycle Memory Access  Optimized Code Generation  Low Power Consumption  Flexible Clocking Scheme  20 to 100 pins  M16C Platform  Low EMI  Low EMS 8. Short Time to Market  Outstanding Development Environment

5. © 2009 Renesas Technology America, Inc. 5 Flash Size (KB) Pin Count R8C Line-up R8C Series GP & ASSP Microcontrollers GP & ASSP Microcontrollers R8C Series  Broad Line-up –From 2KB to 128KB Flash; 20 to 100-pin packages  Extensive Product Offering –General Purpose, Application Specific and LCD Controllers Scalable Architecture (1.8 to 5.5V) 3x 1x2x (2.2 to 5.5V) LCD Microcontrollers LCD Microcontrollers (1.8 to 5.5V) LX (2.7 to 5.5V)

6. © 2009 Renesas Technology America, Inc. 6 R8C/3x Optimized Pin Configuration  No trace crossings  Multiple Package Sizes Scalable Architecture

7. © 2009 Renesas Technology America, Inc. 7 M16C Platform  R8C Family belongs to the Extensive ‘M16C Platform’  Compatible to an extensive number of microcontrollers  Comprehensive scalability  Multitude of options and levels of integration  Common set of development tool environment Scalable Architecture

9. © 2009 Renesas Technology America, Inc. 9 16 Bit CPU Architecture R8C Family CPU Core INTBL PC 0 20 ISP FLG SB USP 0 15 Hardware Multiplier R0HR0L R1HR1L R2 R0HR0L R1HR1L R2 R3 FB A0 A1 FB 0 15 R0HR0L R1HR1L R2 R3 FB A0 A1 0 15 R0HR0L R1HR1L R2 R3 A0 A1 FB 0 15 SWITCH Dual Register Banks Relocatable Interrupt Vector Table Up to 1MB addressable Memory Space Fast 16-bit Multiplication Two Stack Pointer Registers R2 R3 32-bit Configuration B0 B1 Address Data Frame Base Static Base Single-cycle Memory Access + Powerful Configure/Status

10. © 2009 Renesas Technology America, Inc. 10 Efficient Code Generation  Versatile Instruction Set (89 instructions)  Memory-to-memory, register-to-memory, and register-to-register operations  Frequently used instructions (MOV, ADD, SUB, JMP) are 1-byte long  Instructions suited for C language — stack frame manipulation (ENTER, EXIT)  4-bit transfer instructions (MOVLL, MOVHL)  Powerful Bit-manipulation Instructions  BNOT, BTST, BSET, etc.  Fast Instruction Execution Time  20 instructions execute in 1 cycle  Powerful Mathematical Instructions (DSP functionality)  RMPA performs sum of product calculations  SMOVB moves string of data from one area to another in 5 cycles  Eight General and Six Special Addressing Modes  Immediate, Absolute, Static Base Relative, 32-bit Register Direct, etc.  Efficient, Optimized C Compiler Register architecture & Efficient instruction set Efficient, optimized C compiler Fast and compact code R8C CPU Core Powerful

11. © 2009 Renesas Technology America, Inc. 11 Data Transfer Controller (DTC)  Activation sources: all peripheral interrupts, or software  Interrupt generation  Byte or Word transfers  Transfer Modes: Normal and Repeat (fixed address or automatic address increment)  Many virtual HW channels which can also be chained … Control file (for Ch24) RAM for DTC DTC source destination 2 Trigger 1 Interrupt (for Ch2) from peripheral etc. Control registers Data Buffer Control file (for Ch1) 4 Load Control File to Control Register Control file (for Ch2) 5 Read Data from source 6 Write data to destination 7 Write back Control File after transferring ROM/RAM Example: >60% Performance Increase Transfer of 4-channel A/D conversion results to RAM using single sweep mode........ DTC Source 64 DTC Source 1 3 Read DTC vector to determine control data DTC Source 2 Powerful

12. © 2009 Renesas Technology America, Inc. 12 Power-Reduction Techniques Efficient  Flexible clocking scheme -5 system clock sources -Programmable clock dividers -Independent module clocking  Module Standby -Independent shut off of peripheral module -A/D Vref cut-off option  On-chip power management -Three main operating modes: Normal, Wait, Stop Clock Configuration (Simplified) Power can be reduced by up to 1/12,500 of full-speed level Wait: 32kHz (XCIN) High Speed: 20MHz (XIN) 1 Normalized Power Levels High speed: 10MHz/8 (HS OCO) Low speed: 125kHz/8 (LS OCO) Low speed: 32kHz (XCIN) Stop Mode 1/4 1/77 1/33 3 1/4,500 1/12,500 Wait: 32kHz (XCIN) AVss Off Vref Vref Cut-Off A/D Converter Resistor Ladder Analog input

13. © 2009 Renesas Technology America, Inc. 13 Integration of System Components Data Flash with Back Ground Operation (BGO) Data Flash Versatile Level Selection Circuit (16 Levels) Level Selection Circuit (4 Levels) Comparator & Voltage Detection Logic Internal Voltage Reference Reset / Interrupt Power-On Reset & Low- Voltage Detection Circuit LVCMP2 pin VCC High Accuracy 40MHz On-chip Oscillator % Accurac y 2.23.34.55.5 Vcc (V) 5 - 5 Typical MCU R8C -20-100+25+40+85 Temp (C) +/- 2 % - 1 1

15. © 2009 Renesas Technology America, Inc. 15 Rich Functionality Communication Display Analog Processing Analog Processing Timing Control Timing Control I/O Signal Generation Signal Generation Networking  UART, Clock Synchronous  I 2 C, SSU  Comparators  ADC  DAC  8-, 16-bit Multi- function Timers  RTC  LIN  CAN  Segment and Dot matrix LCD Controller  Direct LED Drive  Internal pull-ups Peripherals  PWM Signals  One-shot pulses Versatile

16. © 2009 Renesas Technology America, Inc. 16 CAN (Control Area Network)  FullCAN (Extended CAN) controller compatible with CAN 2.0A and 2.0B specifications  Supports 11- or 29-bit message identifiers for over 500 million unique ID’s  Re-transmission Abort function prevents a message that is lost during arbitration  Listen-Only mode to reuduce bus congestion  16 configurable buffers for efficient data management  Acceptance filter hardware provides message pre-screening mechanism for increased network reliability and decreased CPU overhead  Forced Bus-Off Restore function for quick state recovery Versatile

17. © 2009 Renesas Technology America, Inc. 17 Hardware LIN (Local Interconnect Network)  Generates the Synch Break pulse  Measures the Synch Field duration  Controls Synch Break and Synch Field signal inputs to the UART  Detects bus collisions and can respond in a single bit time and back off without corrupting data Example Application Building Automation Versatile

18. © 2009 Renesas Technology America, Inc. 18 Advanced Analog Functions  2.2uS conversion times at 10-bit resolution  Up to eight conversion result registers  Advanced operation modes: Repeat and Sweep (automatic scan)  Software and Hardware triggers (Timers, external, DTC)  Internal voltage reference available as input ModeNo. of ChannelsHow oftenGenerate INT On One ShotAny one channelOnceComplete Repeat Mode 0Any one channelRepeatedlyNever Repeat Mode 1Any one channelRepeatedlyComplete Single Sweep Mode2/4/6/8 channelsOnceComplete Repeat Sweep Mode2/4/6/8 channelsRepeatedlyComplete ADC Buffer 10-bit x 8 ch...... 1 ANI 0 2 3 ANI n Internal Voltage Reference (1.34V +/- 0.1V) Versatile

19. © 2009 Renesas Technology America, Inc. 19 Powerful Timer Array  7 different types of 8-bit and 16-bit timers  Functions include waveform generation, PWM, time measurement, Real-time clock and more Example Application: Brushless DC Motor Control Versatile

20. © 2009 Renesas Technology America, Inc. 20 Internal LCD voltage booster capable of driving 3V or 5V glass with 1.8V supply Up to 52 Segment lines and 8 Common lines for a maximum of 416 LCD segments 1/2, 1/3 and 1/4 Bias options (internal or external configuration) Automatic Blink Function for each segment independently Multiple clock sources including 32kHz Sub-clock Dedicated LCD RAM area for display and control of each segment All SEG and COM pins are multiplexed with GPIO LCD Controller Versatile

21. © 2009 Renesas Technology America, Inc. 21 Interactive I/O Configuration  Read actual pin state even when pin is in output mode  High/Low Drive Capacity  Balance EMI and Drive Requirements  Output Latches  Avoid Read-Modify-Write Issues  Three Input Thresholds  0.5Vcc, 0.35Vcc, 0.7Vcc  Minimize ground bounce impact  Individually controlled Pull-ups on all ports Output Latch Input Level Switch Drive Capacity Selection Output Driver Pin Input Pull-up Selection Pin State Detection Versatile

23. © 2009 Renesas Technology America, Inc. 23 1-Wire On-Chip Debugging Interface  True 1-Wire Communication I/F  Real-time memory access via Debug DMA  Dedicated Clock for Debug Engine  On-chip Trace  8 Instructions and 1 Data Breakpoint  Up to 255 SW Breakpoints when using HEW Break Before execution Data break Break Trace mode Trace info Trace condition RAM memory reference/change Address match: 4/2 1 On-chip trace Branch destination: 4 No Refer by monitor program during non-run Address match: 8 1 On-chip trace Branch destination/data access: 8 Combination of 2 points Refer during user program execution (run) (RAM trace) R8C/3xA, LxR8C/2x Versatile

24. © 2009 Renesas Technology America, Inc. 24 Fail-Safe Features Oscillator Stop Detection Enhanced Watchdog TimerSystem Operation Access Control Reliable

25. © 2009 Renesas Technology America, Inc. 25 Power Supply Monitoring VCC [V] Vdet0 0 In reset Internal status Vdet1 Vdet2 Low-voltage Detection Interrupt Program execution Power-On Reset In reset (4 options) (16 options) (2 options) Built-in POR & LVD -Power-On Reset circuit can be configured to detect four different voltage levels -Low-Voltage Detect circuit can generate interrupts at 16 different levels set via software -Power supply can also be monitored externally through a pin to trigger LVD interrupts Reliable

26. © 2009 Renesas Technology America, Inc. 26 Excellent Electromagnetic Performance  Careful Vcc and Vss layout  Protection circuits and filters to provide enhanced tolerance for static electricity and help prevent circuit latch-ups  Oscillator switching circuits to reduce noise radiated from clock driver  Advanced chip layout techniques Noise Filters on Input Signals Careful Vcc and Vss Layout Advanced chip layout techniques Techniques to reduce EMI and EMS: Quiet

27. © 2009 Renesas Technology America, Inc. 27  ROM Code Protect bits prevent reading or rewriting of the on-chip flash memory when using a parallel programmer.  Flash Memory ID Code protection feature prevents unauthorized access. The multi-byte ID sent by the serial programmer must match the ID previously set by the user in order to access the flash memory.  Data Protect Function to enable and disable programming or erasing of each flash memory block.  Programmer Mode: MCUs can be programmed using an external box such as a parallel programmer or debug emulator.  Boot Mode: Built-in boot loader program allows PC connection through RS232 interface for easy programming.  CPU/User Mode: Customer can develop custom bootloader program to rewrite the flash memory. The rewrite program can be transferred to RAM when all flash memory contents need to be changed. Trusted & Flexible Advanced Flash Memory Technology

29. © 2009 Renesas Technology America, Inc. 29 Revolutionary Evaluation Platform Short Time to Market

30. © 2009 Renesas Technology America, Inc. 30 Outstanding Development Environment EvaluationEvaluation ProductionProduction DevelopmentDevelopment Production Programming using Renesas’ own Factory Programming Services, or 3 rd -party tools Renesas HEW (High Performance Embedded Workshop) and Advanced Debugging Hardware Code Generator and Evaluation / Starter Kits Short Time to Market

31. © 2009 Renesas Technology America, Inc. 31 R8C (non-LCD) Line-up * On-chip Oscillator Contact Renesas for latest R8C Line-up 20 32 52 64 80 Pins 48 24 R8C/2A,2B R8C/2C,2D 48KB-128KB 8KB-16KB R8C/28,29 8KB-32KB R8C/26,27 R8C/24,25 16KB-64KB R8C/22,23 32KB-128KB R8C/20,21 8KB-16KB CAN D/A 20-ch ADC D/A R8C/2H R8C/2J 16KB-32KB 4KB-8KB 2KB-4KB R8C/2K,2L R8C/2E,2F R8C/2G Automotive Grade Avail. New ASSP’s Low-end R8C’s Lighting Motor Motor Timers, LIN, CAN, 40MHz OCO * Expanded Line-up, D/A, ASSP’s … R8C/32xR8C/32x R8C/36xR8C/36x R8C/38xR8C/38x R8C/33xR8C/33x R8C/35xR8C/35x 4KB-16KB 4KB-32KB 16KB-128KB 32KB-128KB R8C/3GxR8C/3Gx 8KB-32KB R8C/36xR8C/36x CAN R8C/36xR8C/36x 64KB-128KB CAN 64KB-128KB R8C/34xR8C/34x 16KB-32KB Enhanced Performance And Features R8C/3x  R8C/38xR8C/38x R8C/38xR8C/38x R8C/34xR8C/34x CAN R8C/34xR8C/34x 32KB- 128KB

32. © 2009 Renesas Technology America, Inc. 32 R8C/Lx (LCD Controller) Series Line-up Flash Size (KB) 128649648 52 64 80 100 Pins 24 Seg x 4 Com 32 Seg x 4 Com 28 Seg x 8 Com 48 Seg x 4 Com 44 Seg x 8 Com 56 Seg x 4 Com 52 Seg x 8 Com R8C/L357 R8C/L367 R8C/L387 R8C/L358 R8C/L368 R8C/L388 R8C/L3A7R8C/L3A8 R8C/L35A R8C/L36A R8C/L38A R8C/L3AA R8C/L35C R8C/L36C R8C/L38CA R8C/L3AC Contact Renesas for latest R8C Line-up

33. © 2009 Renesas Technology America, Inc. 33 R8C Family Roadmap Introduction in 2009-2010 In Production Function / Performance R8C/Lx “High Performance, LCD Controller” R8C/3x “High Performance” Next:  Super Low Power  Low pin Count  More ASSP’s R8C/1x-2x “General Purpose, Low-Power, ASSP’s”

34. © 2009 Renesas Technology America, Inc. 34 R8C’s Possibilities Building Automation HVAC, Lighting, AMR, Security, Elevators/Escalators Industrial Control Sensors, Pumps, Conveyor Belts, Fans, Actuators R8C Solutions Transportation / Automotive Automotive, Industrial & Recreation Vehicles Computing & Networking Monitoring, Fan control, Power Supply, User Interface, COM I/Fs White Goods / Appliance Motor Control, User Interface, Temperature Control Medical Devices Fertility probes, glucose meters, blood pressure monitor, thermometers

36. © 2009 Renesas Technology America, Inc. 36 Course Summary  Key requirements of 8-bit applications  How R8C Family MCUs fit in the Renesas product portfolio  Top 8 Reasons favoring the use of these MCUs for new 8-bit embedded system designs  Introduction to R8C Line-up and Groups  Future of the R8C Family and Possibilities For more information, please visit our Web site: http://america.renesas.com