1. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Prof. Dirk Timmermann, Claas Cornelius, Stephan Kubisch, Frank Sill, and Harald Widiger Course and contest Student: Enrico Daum

2. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design optimization reduce register- stages !!! 8 stages left ( - 53 %) array of Carry Save Adders with last stage: Ripple Carry Adder fully pipelined (17 stages) RCA = weak point reminder

3. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Register Retiming: performs optimization of sequential logic by moving registers through combinational logic to optimize timing with minimum area impact command optimize_registers Design Compiler Ultra (DC ultra) (1)

4. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Global logic structuring: can reduce logic by factoring out subfunctions and converting them into intermediate variables Constant propagation: propagates logic constants (0/1) through combinational logic and eliminates redundant gates Deletion of unconnected gates: deletes gates with unloaded output pins. Design Compiler Ultra (DC ultra) (2)

5. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Critical path resynthesis (CPR): group and re-implement (structured/mapped) to improve timing. Gate sizing: gates on the critical paths are upsized to improve performance. Gates off of the critical paths are downsized to recover area. command set_compile_directives Design Compiler Ultra (DC ultra) (3)

6. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design results + 1.2% - 24.6%

7. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design results + 188.6%

8. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design conclusion & problems removing overheaded register stages and the use of the DC Ultra leads to meet optimized ? timing requirements But: the use (try out) of the set of optimization techniques takes alot of simulation time