1. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Conditional-Sum-Adder Conditional-Sum-Adder 3rd Meeting: SYNOPSYS Peter Kröger, Peter Danielis Course and contest 2005

2. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Selected options for optimization Optimization only for speed Power and area only determined for last step Selected optionResult (adder_top) frequency = 550 MHz compile –exact_map –ungroup_all Data arrival time: 1,78 ns 561,8 MHz frequency = 550 MHz -boundary_optimization compile –exact_map -boundary_optimization –ungroup_all Data arrival time: 1,78 ns 561,8 MHz frequency = 550 MHz –map_effort high compile –exact_map –map_effort high -boundary_optimization –ungroup_all Data arrival time: 1,76 ns 568,2 MHz frequency = 800 MHz compile –exact_map –map_effort high -boundary_optimization –ungroup_all Data arrival time: 1,19 ns 840,34 MHz frequency = 900 MHz set_ultra_optimization -force compile –exact_map –map_effort high -boundary_optimization –ungroup_all Data arrival time: 1,07 ns 934,58 MHz

3. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Selected options for optimization Selected optionResult (adder_top) frequency = 2500 MHz synthetic_library = dw_foundation.sldb, dw_prefer_mc_inside = true, partition_dp Not feasible! compile –exact_map -boundary_optimization –ungroup_all Data arrival time: 0,40 ns 2500,00 MHz frequency = 995 MHz set_ultra_optimization -force compile –exact_map –map_effort high -boundary_optimization –ungroup_all ------------------------------------------------------------------------------------------------------ Tools Design Optimization: More Map Options Incremental Mapping, Prioritize Min Paths ------------------------------------------------------------------------------------------------------ Without Prioritize Min Paths Data arrival time: 1,01 ns 990,1 MHz ----------------------------- Data arrival time: 0,99 ns 1010,1 MHz ----------------------------- No improvement

4. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Final results Exclusion of Low-Power- and slow cells after analysis of design: set_dont_use {umcl18u250t2_typ/…} etc. Data arrival time: 0,96 ns 1041,7 MHz Total dynamic power: 450,1357 mW Cell leakage power: 10,2760 mW Comb. area: 1031813,9375 square microns