1. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Conditional-Sum-Adder Conditional-Sum-Adder 4th Meeting: SYNOPSYS Peter Kröger, Peter Danielis Course and contest 2005

2. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Selected options for optimization Optimization only for speed (frequency = 2000 MHz) Power and area only determined for last step Selected optionResult (adder_top) set_max_delay 0.0 -from all_inputs() -to all_outputs() compile –exact_map –map_effort high –ungroup_all Tools Design Optimization: More Map Options Incremental Mapping, Prioritize Min Paths Data arrival time: 1.01 ns 990.1 MHz set_max_delay 0.0 –from all_inputs -to all_outputs() –incremental compile –exact_map –map_effort high –ungroup_all –incremental Tools Design Optimization: More Map Options Incremental Mapping Data arrival time: 0.96 ns 1041.7 MHz set_max_delay 0.0 –from all_inputs -to all_outputs() –incremental_mapping compile –exact_map –map_effort high –ungroup_all –incremental_mapping Data arrival time: 0.96 ns 1041.7 MHz Varying capacitance and fanout set_min_capacitance x1 all_inputs() all_outputs() set_max_capacitance x2 all_inputs() all_outputs() set_min_fanout y1 all_inputs() set_max_fanout y2 all_inputs()

3. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Selected options for optimization Min. capacitanceMax. capacitanceMin. fanoutMax. fanoutData arrival time 4164 1.71 ns 48481.58 ns 44441.43 ns 88881.40 ns 16 1.47 ns -16- 1.37 ns -8-8 -4-4 -2-21.58 ns -1-1

4. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Selected options for optimization Selected optionResult (adder_top) set_resource_allocation constraint_driven set_resource_implementation constraint_driven Data arrival time: 1.47 ns 680,3 MHz set_ultra_optimization true -force set_resource_allocation constraint_driven set_resource_implementation constraint_driven set_flatten true -effort high -minimize single_output –flatten compile –exact_map –map_effort high –flatten Data arrival time: 1.03 ns 970,9 MHz set_ultra_optimization true -force set_flatten true -effort high -minimize single_output –area_effort none compile –exact_map –map_effort high –flatten –area_effort none Data arrival time: 0.96 ns 1041.7 MHz Multiple call of the compile-command compile_new_boolean_structure = true set_structure true –timing true –boolean true –boolean_effort high compile_use_fast_sequential_mode = true No improvement

5. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Final results (Perhaps) Modification of the VHDL-File Other cells New structuring Data arrival time: 0,96 ns 1041.7 MHz Total dynamic power: 450.1357 mW Cell leakage power: 10.2760 mW Comb. area: 1031813.9375 square microns Outlook