1. Institut für Angewandte Mikroelektronik und Datentechnik Fachbereich Elektrotechnik und Informationstechnik, Universität Rostock 05.07.2005 VLSI - Adder - Contest Final Report Markus Hempel

2. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Structure of adder Minimum Depth Bounded Tree Prefix Structure design ideas: – high parallelism – few wires low capicitance fast effective routing – trade off between max F OUT and # LEVEL # LEVEL = log 2 n max F OUT = log 2 n # NODS = 56 max (# calc / bit) = 3

3. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Starting point last meeting AddertypeSpeed in Synopsys Speed in SE ratiopower MDBPS1.00 ns6.12 ns 16.3% 25.12µW Why so bad result? broken width constraint due to very bad clock placement independent from core size and place- and route-options Solution: CTS and / or postroute-optimization solved the problem

4. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Design steps 1.Analyse behavior width- constraint error 2.Checking influence of place & route options 3.CTS 4.Resizing core 5.Resizing core asynchronously 6.Special options / parameters

5. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design List of all Values Value Name of design Best frequency : 754.7 MHz MDBPS Best area: 2.608 E4µm² MDBPS Best power@50MHz 8.1024 µW MDBPS Best PDP 162.1pJ MDBPS Name of designer:Markus Hempel Name of Design max. delay [ns] max. frequency f max [MHz] Power Dissipation @ f max [µW] PDP [fJ] Core-Area [µm²] Power Dissipation @ 50 MHz [µW] MDBPS1.325754.7122.34162.12.608 E48.1024

6. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Snapshot – cell power dissipation

7. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Snapshot – cell voltage drop

8. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design More facts of my design PDP = 162.1p J EDP = 214.8 Js core utilisation = 76 % Further optimizations : VHDL level: reduce number of gates Layout level: move critical gates / flipflops from area with high voltage drop