1. Gheorghe M. Ştefan http://arh.pub.ro/gstefan/ - 2014 -

2. BASIC CMOS CIRCUITS see Appendix: Basic circuits Actual digital signals CMOS switches Gates: Inverter (NOT) NAND and NOR gates AND-NOR gates Many-input gates Tristate buffer Transmission gate Flip-Flops 2014Digital Integrated Circuits - week three2

3. Actual signals 2014Digital Integrated Circuits - week three3 V DD evolved from 5V to 1V V Hmin = V Lmax is impossible, because equality is impossible V Hmin > V Lmax is a must

4. Forbidden region 2014Digital Integrated Circuits - week three4

5. Noise margin 2014Digital Integrated Circuits - week three5 N M0 = V IL – V OL N M1 = V OH - V IH

6. CMOS switches z : hi-impedance 2014Digital Integrated Circuits - week three6

7. MOS as switching device C GS = C OX LW R ON = 1/(  n C OX (W/L)(V GS – V T )) 2014Digital Integrated Circuits - week three7

8. NOT: the inverter circuit Static behavior region A: X = 0 region B & C: transition region D: X = 1 2014Digital Integrated Circuits - week three8

9. Dynamic behavior t pHL : time from V OH to V OH /2 t pLH : time from 0 to V OH /2 2014Digital Integrated Circuits - week three9

10. Load capacitance, C L Load capacitance has three components: The intrinsic capacitance of the driver inverter: parasitic drain/bulk capacitance, C DB Wire capacitance: C wire = C thickox L wire W wire Input capacitance of the receiver inverter: C G = C Gp + C Gn = C ox (W p L p + W n L n ) C L = C DB + C wire + C G For long wires connecting the driver to receiver C wire dominates the value of C L 2014Digital Integrated Circuits - week three10

11. t pHL : discharging CL at the constant current I DS(sat) t r - : pMOS lin, nMOS cut t r + : pMOS cut, nMOS sat t r + to (t r +t pHL ): C L discharges at the constant current I Dn(sat) I Dn(sat) =(  n C ox (W n /L n )(V OH –V Tn ) 2 )/2 dv out /dt = -I Dn(sat) /C L = (V OH /2 - V OH )/t pHL t pHL = C L R ONn (1/(1-(V Tn / V OH ))) t pHL = k n C L R ONn t p = (t pHL + t pLH )/2 2014Digital Integrated Circuits - week three11

12. Buffering From t pHL/LH = k n/p C L R ONn/p t p = t 0 (W load /W driver ) t 0 is t p for W load =W driver What is the solution for W load >> W driver ? t p(buffered) = t p0 (W 1 /W driver + W 2 /W 1 + W load /W 2 ) 2014Digital Integrated Circuits - week three12

13. Designing rule for buffering The delay introduced by the new inverters must be minimal: (W 2 /W 1 + W load /W 2 )’ = 0 W 2 = (W 1 W load ) 1/2 W 2 /W 1 = W load /W 2 = (W load /W 1 ) 1/2 The ratio of successive W must be constant Example: let be W load /W driver = n, then W 1 /W driver = W 2 /W 1 = W load /W 2 = n 1/3 For n=1000, results the acceleration: α = t p(no-buffer) /t p(buffered) = (n 2 ) 1/3 /3 = 33.3 2014Digital Integrated Circuits - week three13

14. Power dissipation Switching energy: charging & discharging C L Short-circuit energy: non-zero rise/fall times of the signal Leakage current energy: important for L < 65nm 2014Digital Integrated Circuits - week three14

15. Switching power During each period, T, each capacitor is charged to V DD through R ONp with Q L = C L V DD is discharged to 0 through R ONn The energy to move Q L from V DD to 0 is V DD Q L then: p switch = (V DD C L V DD )/T = C L V 2 DD f clock 2014Digital Integrated Circuits - week three15

16. Short-circuit power Depends on the saturation current p sc = I DD(mean) V DD 2014Digital Integrated Circuits - week three16

17. The leakage current Increase exponentially with temperature Increases exponentially with reduction in V T Dominated by the sub-threshold leakage p leakage = I leakage V DD 2014Digital Integrated Circuits - week three17

18. The NAND gate For both input 1, the output is 0 For at least one input 0 the output is 1 For  n  1.7  p, and W n = W p What is the fastest transition? What is the slowest transition? 2014Digital Integrated Circuits - week three18

19. The NOR gate For both input 0, the output is 1 For at least one input 1 the output is 0 For  n  1.7  p, and W n = W p What is the fastest transition? What is the slowest transition? What do you prefer, NANDs or NORs? 2014Digital Integrated Circuits - week three19

20. Switching activity 2014Digital Integrated Circuits - week three20 Switching activity, σ, on the gate’s output depend on the logic function p switch = C L V 2 DD f clock => p switch = σC L V 2 DD f clock σ : probability of switching from 0 to 1 For 2-input AND: σ = P OUT-0 P OUT-1 = (1-P A P B )P A P B Conservative estimate for big systems: σ = 1/8. Usually is measured: σ = 1/10

21. Glitching The activity to the output of a logic circuit depends also by the propagation time. If ABC switches from 010 to 111 Then O2 does not change according to the logic, but it actually glitches. Dangers: The glitch can be latched Increases the energy consumption 2014Digital Integrated Circuits - week three21

22. Many-input gates t pmax(one-level) ~ 8×n×C in t pmax(log-level) ~ 2×2×C in + 2×n×C in 2014Digital Integrated Circuits - week three22

23. AND-NOR gates Logic: depth = 3, size = 7 Electric: depth = 1, size = 4 Similar approach for: (A + BC)’, (A(B+C))’, … 2014Digital Integrated Circuits - week three23

24. Home work 3 Problem 1: compute α for W load /W driver = 1000 when between driver NOT and load NOT 4 inverter circuits are inserted. Problem 2: compute σ for a 2-input NOR gate and for a 2- input XOR gate. Problem 3: draw, using 3 CMOS pairs, the circuit which performs the function (A(B+C))’. Problem 4: design an asynchronously reset-able (RST) and preset-able (SET) DF-F. (Problem 5: design a synchronously reset-able DF-F.) 2014Digital Integrated Circuits - week three24