1. Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line Scenarios Repeaters in Wiring

2. Previously Transmission line (LC wire) reflection Unbuffered RC wire delay scales as L 2 –0.5 R wire C wire –0.5 L 2 R u C u Penn ESE370 Fall2012 -- DeHon 2

3. Today Transmission Line Scenarios RC (on-chip) Interconnect Buffering Penn ESE370 Fall2012 -- DeHon 3

4. Transmission Line Data travels as waves Line has Impedance May reflect at end of line Penn ESE370 Fall2012 -- DeHon 4

5. Impedance Change What happens if there is an impedance change in the wire? Z 0 =75 , Z 1 =50  –What reflections and transmission do we get? Penn ESE370 Fall2012 -- DeHon 5

6. Z 0 =75, Z 1 =50 At junction: –Reflects V r =(50-75)/(50+75)V i –Transmits V t =(100/(50+75))V i Penn ESE370 Fall2012 -- DeHon 6

7. Impedance Change Z 0 =75, Z 1 =50 Penn ESE370 Fall2012 -- DeHon 7

8. What happens at branch? Penn ESE370 Fall2012 -- DeHon 8

9. Branch Transmission line sees two Z 0 in parallel –Looks like Z 0 /2 Penn ESE370 Fall2012 -- DeHon 9

10. Z 0 =50, Z 1 =25 At junction: –Reflects V r =(25-50)/(25+50)V i –Transmits V t =(50/(25+50))V i Penn ESE370 Fall2012 -- DeHon 10

11. End of Branch What happens at end? If ends in matched, parallel termination –No further reflections Penn ESE370 Fall2012 -- DeHon 11

12. Branch Simulation Penn ESE370 Fall2012 -- DeHon 12

13. Branch with Open Circuit? What happens if branch open circuit? Penn ESE370 Fall2012 -- DeHon 13

14. Branch with Open Circuit Reflects at end of open-circuit stub Reflection returns to branch –…and encounters branch again –Send transmission pulse to both Source and other branch Sink sees original pulse as multiple smaller pulses spread out over time Penn ESE370 Fall2012 -- DeHon 14

15. Open Branch Simulation Penn ESE370 Fall2012 -- DeHon 15

16. Open Branch Simulation Penn ESE370 Fall2012 -- DeHon 16

17. Bus Common to have many modules on a bus –E.g. PCI slots –DIMM slots for memory High speed  bus lines are trans. lines Penn ESE370 Fall2012 -- DeHon 17 http://en.wikipedia.org/wiki/File:DIMMs.jpg

18. Multi-drop Bus Ideal –Open circuit, no load Penn ESE370 Fall2012 -- DeHon 18

19. Multi-Drop Bus Impact of capacitive load (stub) at drop? –If tight/regular enough, change Z of line Penn ESE370 Fall2012 -- DeHon 19

20. Multi-Drop Bus Long wire stub? –Looks like branch may produce reflections Penn ESE370 Fall2012 -- DeHon 20

21. Transmission Line Noise Frequency limits Imperfect termination Mismatched segments/junctions/vias/connectors Loss due to resistance in line –Limits length Penn ESE370 Fall2012 -- DeHon 21

22. Idea Transmission lines –high-speed –high throughput –long-distance signaling Termination Signal quality Penn ESE370 Fall2012 -- DeHon 22

23. Back to RC Wire (on-chip, no L) Penn ESE370 Fall2012 -- DeHon 23

24. Delay of Wire Long Wire: 1mm R wire = 60K  for the 1mm) C wire = 0.16 pF  for the 1mm) Driven by inverter –R 0 = 25K  –C 0 = 0.01 fF –Assume velocity saturated, sized W p =W n =1 Loaded by identical inverter Penn ESE370 Fall2012 -- DeHon 24

25. Formulate Delay Penn ESE370 Fall2012 -- DeHon 25 Delay of inverter driving wire? Should be able to do these calculations on final.

26. Calculate Delay C load = 2 C 0 R buf = R 0 C self =  2 C 0 = 2 C 0 Penn ESE370 Fall2012 -- DeHon 26

27. Buffer Middle Delay if add buffer to middle of wire? Penn ESE370 Fall2012 -- DeHon 27 Should be able to do these calculations on final.

28. Formulate and Calculate Delay Penn ESE370 Fall2012 -- DeHon 28

29. N Buffers Delay for N buffers? Penn ESE370 Fall2012 -- DeHon 29

30. Minimize Delay How minimize delay? Differentiate & Solve for N: Penn ESE370 Fall2012 -- DeHon 30 Equalizes delay in buffer and wire

31. Calculate: Delay at Optimum Stages for Example R wire = 60K  for the 1mm) C wire = 0.16 pF  for the 1mm) R buf =R 0 = 25K  C self =C load =2(C 0 = 0.01 fF)=0.02fF Penn ESE370 Fall2012 -- DeHon 31

32. Segment Length R wire = L×R unit C wire = L×C unit Penn ESE370 Fall2012 -- DeHon 32

33. Optimal Segment Length Delay scales linearly with distance once optimally buffered Penn ESE370 Fall2012 -- DeHon 33

34. Buffer Size? How big should buffer be? –R buf = R 0 /W –C load = 2 W C 0 (assuming velocity saturation) –C self =  2 W C 0 Penn ESE370 Fall2012 -- DeHon 34

35. Implication W R wire = L×R unit C wire = L×C unit  W independent of Length –Depends on technology Penn ESE370 Fall2012 -- DeHon 35

36. Delay at Optimum W With  =1, 1+  =2 Same size as first term Penn ESE370 Fall2012 -- DeHon 36

37. Ideas Wire delay linear once buffered Optimal buffering matches –Buffer delay –Delay on wire between buffers Penn ESE370 Fall2012 -- DeHon 37

38. Admin Final – Friday 12/14, noon, Moore 212 Review – Wednesday, 12/12 –Evening – time announced on piazza Andre out of town until Friday Penn ESE370 Fall2012 -- DeHon 38