1. October 10, 20001

2. 2 USB 2.0 Hub Additions John Garney Chair Hub Working Group Intel Corporation John Garney Chair Hub Working Group Intel Corporation

3. October 10, 20003 Hub Additions w Standard Hub Class – Port Indicators w Transaction Translator w Bulk/Control Transaction Handling w Isochronous/Interrupt Transaction Handling w Scheduling Split Transactions w Additions to Chapter 11 w New Appendices

4. October 10, 20004 Hub Requirements: w Provide high-speed expansion w Isolate full/low-speed from high-speed – Avoid lower speed impact on HS, i.e., LS impact on FS w All USB2.0 Hub ports support HS/FS/LS w Optional: standardized port indicators (LEDs)

5. October 10, 20005 System SW Client Driver USB 1.1 Device HS Hub USB 1.1 Hub USB 1.1 Device HS Device USB 2.0 Host Controller Controller Full/Low Speed High Speed Only (2 x 12Mb/s Capacity) Hub In High Speed System w Hub provides high-speed expansion (ala 1.1 hub) w Hub provides additional classic bus(es) – Same total number of devices per USB2.0 Host Controller (e.g. 127) w Greater end user value than classic hub – Performance, expansion and ease of use w Hub is user selected device (not required for all systems)

6. October 10, 20006 Reuse Classic Hub Design Knowledge Reuse Classic Hub Design Knowledge HS/Classic Hub State MachineHS/Classic Machine HS/Classic Hub Repeater Repeater Controller Controller High Speed Only Port Hub “Classic Pieces” w Repeater – High speed signaling u Also, FS/LS signaling for 1.1 compatibility – Reclocking w State Machine – HS termination sequencing u HS Detect, Reset, Suspend, Resume w Hub Controller – Respond to hub device class requests/events

7. October 10, 20007 Hub Architecture w Same as classic hub: – High & full/low-speed repeaters, determined by upstream facing link – Hub controller – No different then classic USB besides high-speed signaling w Minor changes from classic hub: – Hub state machine (HS detect, HS termination transitions, test mode) w New in hub: – Transaction Translator – Routing logic HS/Classic Hub Controller ControllerTransactionTranslatorTransactionTranslator Full/LowSpeed High Speed Only..... HS/Classic Hub State Machine Machine Routing Logic Port HS/Classic Hub Repeater Repeater

8. October 10, 20008 Routing Logic Routing Logic TransactionTranslatorTransactionTranslator Full/LowSpeed High Speed Only Port Repeater, Controller,... Port Hub New Pieces w Port Routing Logic – Controllable electrical connection between: u Full/Low (Transaction Translator), or u High-Speed (Repeater) – Route done once per device reset w Transaction Translator – Major addition for USB 2.0 – Uses split transaction protocol HC support.....

9. October 10, 20009 Hub Cost / Complexity Estimate w Classic Hub + new things – Classic Hub - implementation dependent, but knowable baseline – New things u Signaling Ô Required for any High-Speed device u Logic (routing, TT) u RAM (buffer space, transaction pipeline) w Total (approximate) – 40KGates + 1800 Bytes with 4 downstream ports – 28KGates + (3KG * # of downstream ports) + 1800 Bytes TT FIFOs TT Logic Port High-Speed “Classic Hub” Port Routing Logic

10. October 10, 200010 Standard Hub Class w Hub Descriptor – Added to wHubCharacteristics : u D6..D5: TT Think Time u D7: Port indicator support w Hub Class Requests – New Port Features: PORT_TEST, PORT_INDICATOR – Get_Status: PORT_HIGH_SPEED – New: ClearTTBuffer, ResetTT, GetTTState, StopTT

11. October 10, 200011 Hub Port Indicators w Optional standardized end user visible indicator w 2 color indicator for each downstream facing port – Defined colors: Off, Green, Amber, Blinking w Manual (Host SW) & Automatic Control – Manual: keeps HW simple while allowing SW control u Blinking done by software – Automatic: basic consistency in USB 1.x/2.0 systems u Overcurrent, enabled and “neither” – Full indicator support requires USB 2.0 software

12. October 10, 200012 Reserved Blinking Amber/Green Hardware Attention Blinking Off/Amber Software Attention Blinking Off/Green Fully Operational Green Error Condition Amber Not Operational OffDefinitionColor Indicator Color Meanings

13. October 10, 200013 Indicator Control w Controlled via SetPortFeature(PORT_INDICATOR, indicator_selector) Value Port Indicator Selector Port Indicator Mode Color set automatically, as defined in following Automatic 1AmberManual 2Green 3Off 4-FFHReservedReserved 0

14. October 10, 200014 Automatic Indicator Control SetPortFeature (PORT_POWER) Automatic Mode OffOff !(Enabled or Transmit or TransmitR) and PORT_OVER_CURRENT != 1 Enabled or Transmit or TransmitR GreenGreen SetPortFeature (PORT_INDICATOR, indicator_selector = 0) or ClearPortFeature (PORT_INDICATOR, n/a) SetPortFeature (PORT_INDICATOR, indicator_selector != 0) ManualMode Amber PORT_OVER_CURRENT = 1

15. October 10, 200015 Host Controller / TT Interactions HostHost DeviceDevice TTTT X X2 TT buffers full/low speed transaction information (X) locally  TT buffers full/low speed transaction information (X) locally 1 – SPLIT-s, OUT, DATAx (Start-split)  Host Controller issues start-split transaction to TT TTTT R R 4 -...,ACK TT buffers full/low speed transaction results (R) locally  TT buffers full/low speed transaction results (R) locally 3 - OUT, DATAx,...  TT issues full/low speed transaction on downstream bus 6 - …,ACK 6 - …,ACK  TT responds with results InterruptOutExample 5 – SPLIT-c, OUT, … (Complete-split)  Host Controller issues complete-split transaction to TT

16. October 10, 200016 Transaction Translator Overview w Bulk/Control & Interrupt/Isochronous portions to TT – Bulk/Control uses USB flow control to make progress – Interrupt/Isochronous uses a scheduled full/low speed transaction “pipeline” – Separate buffers are used for each TT portion u 2 or more transaction buffers for bulk/control u Start & complete “pipeline” buffers for interrupt/isochronous Transaction Translator Bulk & Control Bulk & Control Interrupt & Isochronous Interrupt & Isochronous

17. October 10, 200017 TT Bulk / Control w TT buffers 2 or more bulk/control transactions w TT issues full/low speed transaction when no periodic transactions pending w Host controller issues split transactions to TT – Allows starting/completing full/low-speed transactions each microframe – Normal approach of “bandwidth reclamation” is used – Tries to issue HS start-split; if successful, next attempt does complete-split TTTT Bulk/Ctrl #1 Bulk/Ctrl #2 High Speed Start-/Complete-Split Full/Low Speed Transaction

18. October 10, 200018 Example: Bulk OUT Single Split Trans. TTTT X2  TT buffers full/low speed transaction information (X) locally 3 - OUT, DATAx,...  TT issues full/low speed transaction on downstream bus R R 4 -...,ACK  TT buffers full/low speed transaction results (R) locally 6 - …,ACK 6 - …,ACK  TT responds with results 1 – SPLIT-s, OUT, DATAx, ACK  Host Controller issues start-split transaction to TT 5 – SPLIT-c, OUT,...  Host Controller issues complete-split transaction to TT

19. October 10, 200019 Example Bulk OUT Splits w Assume 2 classic bulk OUT endpoints w Assume (illegal) 1 TT bulk/control buffer w Classic bus has significant idle time HS Bus: Classic Bus: S S SS2a O O D D N N S S SS1a O O D D A A Full SS2a O O D D N N S S CS1a O O Y Y C C Ready SS2a O O D D A A S S Full CS1a O O A A C C Empty Periodic Xacts Empty TT Bulk Buffer: CS2a O O Y Y C C TIME O O D D A A EP1 Transaction O O D … EP2 Transaction

20. October 10, 200020 Example: Bulk OUT Two Different Split Trans. TTTT X 2 3 - OUT, DATAx,...  R R 6 -...,ACK  TT buffers 1st full/low speed transaction results (R) locally 1 – SPLIT-s, OUT, DATAx, ACK  - Same as before  HC issues Start-split transaction for different endpoint to TT 4 – SPLIT-s, OUT, DATAx, ACK x2  TT buffers full/low speed transaction (x2) locally in 2nd buffer 5  TT issues 2nd full/low speed transaction on downstream bus 7 - OUT, DATAx,...

21. October 10, 200021 Example: Bulk OUT Two Different Split Trans. TTTT  TT responds with results from 1st buffer 9 - …,ACK 9 - …,ACK  HC issues complete-split transaction for 2nd endpoint to TT 8 – SPLIT-c, OUT,... r2 10 TT buffers full/low speed transaction results (r2) locally TT buffers full/low speed transaction results (r2) locally 10 -...,ACK R R 12 TT responds with results TT responds with results 12 - …,ACK 12 - …,ACK 11 HC issues complete-split transaction for 2nd endpoint to TT HC issues complete-split transaction for 2nd endpoint to TT 11 – SPLIT-c, OUT,... 11 – SPLIT-c, OUT,...

22. October 10, 200022 Example Bulk OUT Splits w Assume 2 classic bulk OUT endpoints w Always at least 2 TT bulk/control buffers w Most classic bus idle time eliminated HS Bus: Classic Bus: S S SS1a O O D D A A 1 Full 1 Empty Periodic Xacts 1 Ready CS1a O O Y Y C C 1 Empty CS1a O O A A C C SS1b O O D D A A S S 1 Full TT Bulk Buffer: CS2a O O Y Y C C TIME O O D … O O D D A A EP1 Transaction O O D D A A EP2 Transaction S S SS2a O O D D A A 2 Full CS2a O O Y Y C C 2 Ready

23. October 10, 200023 TT Int. / Isoch. Pipeline w Host software budgets when full/low-speed transaction will run w Host schedules start-split before “earliest” start time w Host schedules complete-split at “latest” finish time(s) w Scheduling variation due to bit-stuffing and timeouts, etc. TTTT High Speed Start-Split High Speed Complete-Split Start-splitFIFOStart-splitFIFOComplete-splitFIFOComplete-splitFIFO StartHandlerStartHandlerCompleteHandlerCompleteHandler Full/LowHandlerFull/LowHandler

24. October 10, 200024 TTTT Start-split Start-splitFIFO FIFOComplete-splitFIFOComplete-splitFIFO Full/LowHandlerFull/LowHandler StartHandlerStartHandlerCompleteHandlerCompleteHandler X X2  TT buffers full/low speed transaction information locally 1 – SPLIT-s, OUT, DATAx  Host Controller issues start-split transaction to TT 3 - OUT, DATAx,...  TT issues full/low speed transaction on downstream bus 6 - …,ACK 6 - …,ACK  TT responds with results Example: Int. OUT Split Trans. R R 4 -...,ACK  TT buffers full/low speed transaction results locally Start-split Start-splitFIFO FIFO 5 – SPLIT-c, OUT,... 5 – SPLIT-c, OUT,...  Host Controller issues complete-split transaction to TT

25. October 10, 200025 Scheduling TT Pipeline w Best case budget & worst case operation w Scheduling split transactions for pipeline w Keeping the pipeline running

26. October 10, 200026 Best Full-Speed Budget w Max. 1500 bytes per classic frame (12Mb/s) w Max. 1350 bytes of periodic wire time (90% of frame) w Max. 1157 allocatable bytes w/ max 6/7 (16.67%) bit stuff – Reduced further by other overhead w Max. 187.5 “wire” bytes per 125us microframe – Budget best case of 188 bytes w Best Case Budget assumes wire runs “as fast as possible” Y0Y0Y0Y0 Y1Y1Y1Y1 Y2Y2Y2Y2 Y3Y3Y3Y3 Y4Y4Y4Y4 Y5Y5Y5Y5 Y6Y6Y6Y6 Y7Y7Y7Y7 29188 32187.5 Microframes Best case wire budget,1157 bytes w/ no bitstuffing Max wire time

27. October 10, 200027 Worst Case Operation w Worst case when bus runs “as slow as possible” w 188 “data” bytes can take 220 bytes of time to move w Classic transaction runs in three possible microframes – Due to difference between best & worst case Y0Y0Y0Y0 Y1Y1Y1Y1 Y2Y2Y2Y2 Y3Y3Y3Y3 Y4Y4Y4Y4 Y5Y5Y5Y5 Y6Y6Y6Y6 Y7Y7Y7Y7 Best case wire budget, 1157 bytes w/ no bitstuffing 29188 Microframes 220219 220219 34 Worst case, 1350 bytes w/ max bitstuffing 161161 187 Worst case with bulk reclaim 219 220219 34 162 bytes w Reclamation (LS control) makes it no worse

28. October 10, 200028 Transaction Scheduling w Classic transaction determines HS split-transactions w Allocate time on classic wire for a new transaction: – Calculate best case classic wire budget w Determine schedule for high speed start-split(s) – Based on Best case budget w Determine schedule for high speed complete-split(s) – Based on Best case budget and rules that deal with worst – Don’t compute worst case, use “3” microframes

29. October 10, 200029 Generic Scheduling of Split Transactions w Allocate time for a new transaction (Y-1) 7 Y0Y0Y0Y0 Y1Y1Y1Y1 Y2Y2Y2Y2 Y3Y3Y3Y3 Y4Y4Y4Y4 Y5Y5Y5Y5 Y6Y6Y6Y6 Y7Y7Y7Y7 Best case budget #1: A classic transaction budgeted to run here on the classic bus,... #2: …has a HS start-split scheduled in this microframe and... #2: …has a HS start-split scheduled in this microframe and... HSStart-splitHSStart-split w Start-splits scheduled in microframe “before” Best case classic w Additional scheduling rules for specific cases (see chap 11) w Complete-splits in (roughly) “next 3” microframes #3: …has HS complete-split transactions scheduled in the latest possible microframes for this transaction HS Complete-splits

30. October 10, 200030 Long Isochronous OUT w Isochronous OUT with >188 data payload has: – More start-splits u A start-split for each microframe with budgeted data present u Different PID based on which portion of classic data (begin,mid,end) u Each start-split is scheduled 188 data bytes (except last) – No complete-split(s) (Y-1) 7 Y0Y0Y0Y0 Y1Y1Y1Y1 Y2Y2Y2Y2 Y3Y3Y3Y3 Y4Y4Y4Y4 Y5Y5Y5Y5 Y6Y6Y6Y6 Y7Y7Y7Y7 BeginEndMidMid Best case budget Microframes with HS Start-Splits Long isoch. transaction Start-SplitTokens:

31. October 10, 200031 Keeping the Pipe Running w TT periodic pipeline must continue to sequence – Normally it does, but… – Errors can occur on high/full/low-speed buses w TT must not service full/low-speed transactions: – Too early – Too late w Microframe “clock” tracking is required

32. October 10, 200032 Periodic Pipeline Example w Example full speed transactions: – T1: 187 data byte isoch IN – T2: 376 data byte isoch OUT – T3: 188 data byte isoch IN – T4: 564 data byte isoch IN w Schedule start-splits SSx - Start-splits Tx - Classic transaction CSx - Complete-splits Best Budget: T3T1T2T4 SS3 SS1 SS4SS2aSS2c SS2b

33. October 10, 200033 Pipeline Example w Schedule Complete-splits SSx - Start-splits Tx - Classic transaction CSx - Complete-splits Best Budget: T1T2T4T3 CS3bCS3aCS3cCS1aCS1bCS1cCS4bCS4dCS4cCS4a – Isoch OUT T2 has no complete-splits – Isoch IN T4 only has one additional complete-split

34. October 10, 200034 SS2b SS2cSS3SS4aCS1bdata0CS3aerrCS4amdataCS1amdata TT Response: Actual: SSx - Start-splits Tx - Classic transaction CSx - Complete-splits CS4bmdataCS4cmdataCS4ddata0 Periodic Pipeline Example T1T2 Best Budget: Worst Budget: T3 T1T2T4T3 T4 CS1aCS3b CS4b CS4bCS4dCS1bCS3aCS4aCS4cSS1SS2aSS2cSS3SS4aSS2b SS1SS2a T1 T1 T2T2 T2Bulk T4 T4T4 T4 CS3c

35. October 10, 200035 Example Bus Traces w Split Bulk w Split Interrupt w Split Isochronous

36. October 10, 200036 USB2.0 Hub Additions Summary w Hub Ports Support all Speeds (High/Full/Low) – Isolation of High and Full/Low Speeds via TT u Simultaneous High and Full/Low-Speed Transactions – Full/Low Speed (12Mb/s) bus per TT u Can be TT per hub or TT per port w Hub Class Descriptor & Requests w Optional Standardized Port Indicators w TT Internals – Bulk/Control buffering – Interrupt/Isochronous scheduled pipeline w Host OS Microframe Pipeline Scheduling