1. Verilog Digital System Design Z. Navabi, 2006
RT Level Design
RT level design:
Taking a high level description of a design
Partitioning
Coming up with an architecture
Designing the bussing structure
Describing and implementing various components of the architecture
Steps in RT level design:
Control/Data Partitioning
Data Part Design
Control Part Design
Verilog Digital System Design Z. Navabi, 2006

2. Verilog Digital System Design Z. Navabi, 2006
RT Level Design
Verilog Digital System Design Z. Navabi, 2006

3. Control/Data Partitioning
Verilog Digital System Design Z. Navabi, 2006

4. Control/Data Partitioning
Verilog Digital System Design Z. Navabi, 2006

5. Verilog Digital System Design Z. Navabi, 2006
Data Part
Data Part
Verilog Digital System Design Z. Navabi, 2006

6. Verilog Digital System Design Z. Navabi, 2006
Data Part
Verilog Digital System Design Z. Navabi, 2006

7. Inputs to data part, sent to the data components and busses
Output Signals: Going to the control part, provide flags and status of the data
Data Part
module DataPath
(DataInput, DataOutput, Flags, Opcodes, ControlSignals);
input [15:0] DataInputs;
output [15:0] DataOutputs;
output Flags, ...;
output Opcodes, ...;
input ControlSignals, ...;
// instantiation of data components
// ...
// interconnection of data components
// bussing specification
endmodule
Control Signals:
Inputs to data part, sent to the data components and busses
DataPath Module
Verilog Digital System Design Z. Navabi, 2006

8. Verilog Digital System Design Z. Navabi, 2006
Data Part
Data Component:
Shows how the component uses its input control signals to perform various operations on its data inputs
module DataComponent
(DataIn, DataOut, ControlSignals);
input [7:0] DataIn;
output [7:0] DataOut;
input ControlSignals;
// Depending on ControlSignals
// Operate on DataIn and
// Produce DataOut
endmodule
Partial Verilog Code of a Data Component
Verilog Digital System Design Z. Navabi, 2006

9. Verilog Digital System Design Z. Navabi, 2006
Control Part
Control Part
Verilog Digital System Design Z. Navabi, 2006

10. Control Part
Makes decisions as to when and what control signals to issue depending on its state.
Consists of one or more state machines
to keep the state of the circuit.
Verilog Digital System Design Z. Navabi, 2006

11. Takes control inputs from the
Control Part
module ControlUnit
(Flags, Opcodes, ExternalControls, ControlSignals);
input Flags, ...;
input Opcodes, ...;
input ExternalControls, ...;
output ControlSignals;
// Based on inputs decide :
// What control signals to issue,
// and what next state to take
endmodule
Takes control inputs from the
Data Part
Outline of a Controller
Verilog Digital System Design Z. Navabi, 2006

12. Sequential Multiplier
An add-and-shift
Sequential
Multiplier
Multiplication begins with the start pulse.
When both bytes are outputed.
For the most-significant byte
An 8-bit bidirectional I/O
for inputing it’s 8-bit operands and outputing its 16-bit output one byte at a time.
Multiplier Block Diagram
Verilog Digital System Design Z. Navabi, 2006

13. Sequential Multiplier
Verilog Digital System Design Z. Navabi, 2006

14. Shift-and-add Multiplication Process
Verilog Digital System Design Z. Navabi, 2006

15. Shift-and-add Multiplication Process
Depending on bit i of
operand A, either operand
B is added to the collected
partial result and then
shifted to the right
(when bit i is 1)
Or (when bit i is 0) the
collected partial result
is shifted one place to
the right without being
added to B.
Manual Binary Multiplication
Verilog Digital System Design Z. Navabi, 2006

16. Shift-and-add Multiplication Process
Hardware Oriented Multiplication Process
Verilog Digital System Design Z. Navabi, 2006

17. Shift-and-add Multiplication Process
Because A[0] is 1, the partial
sum of B + P is calculated.
Hardware Oriented Multiplication Process (Continued)
Verilog Digital System Design Z. Navabi, 2006

18. Shift-and-add Multiplication Process
Because A[0] is 0,
P is calculated
The right most bit of
which is shifted into A,
and the rest replace P
Hardware Oriented Multiplication Process (Continued)
Verilog Digital System Design Z. Navabi, 2006

19. Shift-and-add Multiplication Process
The least significant 4 bits of
the multiplication result
become available in A and the
most-significant bits in P.
Hardware Oriented Multiplication Process (Continued)
Verilog Digital System Design Z. Navabi, 2006

20. Sequential Multiplier Design
Verilog Digital System Design Z. Navabi, 2006

21. Sequential Multiplier Design
Verilog Digital System Design Z. Navabi, 2006

22. Control Data Partitioning
Verilog Digital System Design Z. Navabi, 2006

23. Control Data Partitioning
Data part consists of
registers, logic units, and
their interconnecting buses.
On the rising edge of the
system clock, the controller
goes into a new state.
Datapath and Controller
Verilog Digital System Design Z. Navabi, 2006

24. Verilog Digital System Design Z. Navabi, 2006
Multiplier Datapath
Verilog Digital System Design Z. Navabi, 2006

25. Selects carry-out from
the adder or 0 depending
on the value of sel_sum
Multiplier Datapath
Adder
Multiplexer
8-bit Registers
8-bit Shift Register
Tri-state Buffers
Multiplier Block Diagram
Verilog Digital System Design Z. Navabi, 2006

26. Verilog Digital System Design Z. Navabi, 2006
Datapath Description
Verilog Digital System Design Z. Navabi, 2006

27. Verilog Digital System Design Z. Navabi, 2006
Datapath Description
module datapath ( input clk, clr_P, load_P,
load_B, msb_out, lsb_out,
sel_sum, load_A, shift_A,
inout [7:0] data, output A0 );
wire [7:0] sum, ShiftAdd;
reg [7:0] A, B, P;
wire co;
Datapath Verilog Code
Verilog Digital System Design Z. Navabi, 2006

28. 8-bit shift-register for operand A
Datapath Description
Represents
register B
posedge clk ) if (load_B) B <= data;
posedge clk )
if (load_P) P <= {co&sel_sum, ShiftAdd[7:1]};
assign { co, sum } = P + B;
case ( { load_A, shift_A } )
2'b01 : A <= { ShiftAdd[0], A[7:1] };
2'b10 : A <= data;
default : A <= A;
endcase
Represents
the 8-bit adder
Represents register P
for the partial result
Implements the
8-bit shift-register for operand A
Shifts A contents
Loads A with data
Datapath Verilog Code (Continued)
Verilog Digital System Design Z. Navabi, 2006

29. Datapath Description ............................... assign A0 = A[0];
assign ShiftAdd = clr_P ? 8'h0 :
( ~sel_sum ? P : sum );
assign data = lsb_out ? A : 8'hzz;
assign data = msb_out ? P : 8'hzz;
endmodule
Multiplexer for
selection of sum or P
2 sets of tri-state buffers
driving the bidirectional
data bus of the datapath
Datapath Verilog Code (Continued)
Verilog Digital System Design Z. Navabi, 2006

30. Multiplier Controller
Verilog Digital System Design Z. Navabi, 2006

31. Datapath Description `define idle 4'b0000 `define init 4'b0001
The multiplier controller
is a finite state machine
that has 2 starting states,
8 multiplication states,
and 2 ending states.
The multiplier waits for
start while loading A
`define idle 4'b0000
`define init 4'b0001
`define m 'b0010
`define m 'b0011
`define m 'b0100
`define m 'b0101
`define m 'b0110
`define m 'b0111
`define m 'b1000
`define m 'b1001
`define rslt1 4'b1010
`define rslt2 4'b1011
Multiplier loads B
The multiplier performs
add-and-shift of P+B, or
P+0, depending on A0
States and
their binary assignments
The 2 halves of the result
are put on databus.
Multiplier Control States
Verilog Digital System Design Z. Navabi, 2006

32. Multiplier Controller
Declares signals that
connect to datapath ports
Multiplier Controller
module controller ( input clk, start, A0,
output reg clr_P, load_P, load_B, msb_out, lsb_out, sel_sum,
output reg load_A, Shift_A, done);
reg [3:0] current;
( negedge clk ) begin
clr_P = 0; load_P = 0; load_B = 0; msb_out = 0; lsb_out = 0;
sel_sum = 0; load_A = 0; Shift_A = 0; done = 0;
always block to issue
control signals and make
state transitions
All control signal outputs
are set to their inactive values.
Eliminating unwanted
latches that may be
generated by a synthesis
tool for these outputs.
Verilog Code of Controller
Verilog Digital System Design Z. Navabi, 2006

33. Multiplier Controller
The currently active state
of the machine
case ( current )
`idle :
if (~start) begin
current <= `idle;
done = 1;
end else begin
current <= `init;
load_A = 1; clr_P = 1; load_P = 1;
end
`init : begin
current <= `m1;
load_B = 1; end
To clear the P register
To Load A
Verilog Code of Controller (Continued)
Verilog Digital System Design Z. Navabi, 2006

34. Multiplier Controller
`m1, `m2, `m3, `m4, `m5, `m6, `m6, `m7, `m8: begin
current <= current + 1;
Shift_A = 1; load_P = 1;
if (A0) sel_sum = 1;
end
Shifting A
Loading P
Asserting sel_sum
Verilog Code of Controller (Continued)
Verilog Digital System Design Z. Navabi, 2006

35. Multiplier Controller
In the result states,
lsb_out and msb_out
are asserted in two
consecutive clocks in
order to put A and P
on the data bus
respectively.
`rslt1 : begin
current <= `rslt2;
lsb_out = 1;
end
`rslt2 : begin
current <= `idle;
msb_out = 1;
default : current <= `idle;
endcase
endmodule
Verilog Code of Controller (Continued)
Verilog Digital System Design Z. Navabi, 2006

36. Top-Level Code of the Multiplier
Verilog Digital System Design Z. Navabi, 2006

37. Top-Level Code of the Multiplier
module Multiplier ( input clk, start,
inout [7:0] databus,
output lsb_out, msb_out, done );
wire clr_P, load_P, load_B, msb_out, lsb_out, sel_sum, load_A, Shift_A;
datapath dpu( clk, clr_P, load_P, load_B,
msb_out, lsb_out, sel_sum, load_A, Shift_A, databus, A0 );
controller cu( clk, start, A0, clr_P, load_P, load_B, msb_out, lsb_out, sel_sum, load_A, Shift_A, done );
endmodule
Datapath and controller
modules are instantiated.
Top-Level Multiplier Code
Verilog Digital System Design Z. Navabi, 2006

38. Verilog Digital System Design Z. Navabi, 2006
Multiplier Testing
Multiplier
Testing
Verilog Digital System Design Z. Navabi, 2006

39. Multiplier Testing timescale 1ns/100ps module test_multiplier;
reg clk, start, error;
wire [7:0] databus;
wire lsb_out, msb_out, done;
reg [7:0] mem1[0:2], mem2[0:2];
reg [7:0] im_data, opnd1, opnd2;
reg [15:0] expected_result, multiplier_result;
integer indx;
An auto-check
interactive testbench for
the sequential multiplier
A bidirectional bus,
declared as wire for reading
Inputs and outputs
of the multiplier
Declared for writing to the
bidirectional databus
What is calculated
in the testbench
The result read
from the multiplier
Multiplier Testbench Outline
Verilog Digital System Design Z. Navabi, 2006

40. Multiplier Testing
Read data files data1.dat
and data2.dat and apply data to databus
Multiplier uut ( clk, start, databus, lsb_out, msb_out, done );
initial begin: Apply_data end //Figure 8.11
initial begin: Apply_Start ... end //Figure 8.12
initial begin: Expected_Result... end //Figure8.13
clk) begin: Actual_Result ... end // Figure 8.14
clk) begin: Compare_Results...end // Figure 8.15
always #50 clk = ~clk;
assign databus=im_data;
endmodule
Apply start to start multiplication
Calculate the
expected result
Wait for multiplication to complete, and collect the calculated result
Compare expected and
calculated results and issue
error if they do not match
Above tasks are timed
independently, at the same time,
an always block generates a
periodic signal on clk that
clocks the multiplier.
Applies three rounds of test
to the Multiplier module.
In each round, data is applied
to the module under test and
results are read and compared
with the expected results.
Multiplier Testbench Outline
Verilog Digital System Design Z. Navabi, 2006

41. Verilog Digital System Design Z. Navabi, 2006
Multiplier Testing
Verilog Digital System Design Z. Navabi, 2006