1. Spring 2006 1 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering Advanced Computer Architecture Lecture 2 NSD with MUX and ROM Class CPU model

2. Spring 2006 2 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering FSM design Assume: synchronous solution Describe: what your design should do Determine: inputs and outputs Create: state diagram Assign: adjacent states (no glitches) Prepare: next state table Explore: implementation options

3. Spring 2006 3 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering FSM architecture Present State NS Decoder Output Decoder Inputs Outputs Combo logic ROM MUX Combo logic ROM MUX Decoder Flip Flops

4. Spring 2006 4 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering Example design Design a 2-bit, Grey code counter with two control signals: enable, up/down Sequence = {0, 1, 3, 2, 0} NOTE: no output decoder required

5. Spring 2006 5 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering Prepare next state table Inputs Present State Next State Outputs U/DEnableQ1Q0 00110011 01010101 00 10 00 01 01000100 00010001 00110011 01010101 00 01 11 00010001 10111011 00110011 01010101 10 11 10 00 11101110 01000100 00110011 01010101 11 01 11 10 10111011 11101110 Count Up

6. Spring 2006 6 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering Prepare next state table Inputs Present State Next State Outputs U/DEnableQ1Q0 00110011 01010101 00 10 00 01 01000100 00010001 00110011 01010101 00 01 11 00010001 10111011 00110011 01010101 10 11 10 00 11101110 01000100 00110011 01010101 11 01 11 10 10111011 11101110 Count Down

7. Spring 2006 7 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering Next state decoder examples Sum of products (SOP) MUX ROM

8. Spring 2006 8 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering NSD SOP Implementation Two decoders determine the 16 NSD states An OR gate combines all the K-map cells with a 1 –D 0 = {1,3,6,7,9,b,c,d} –D 1 = {2,3,4,6,a,b,d,f}

9. Spring 2006 9 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering Schematic 0 - 7 8 - f Or gates SOP Implementation NSD

10. Spring 2006 10 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering NSD MUX implementation Reduce next state table –For each present state, do K-map on remaining inputs –Reduced K-map contains logic expression Implementation –Connect present state to MUX select lines –Enter logic function on each input

11. Spring 2006 11 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering MUX Example 0 132 4 576 8 9BA C DFE Q1 Q0 IN1 IN0 00 011110 00 01 11 10 1 11 0 0 0 00 0 0 0 0 000 0 S0S0 S1S1 S3S3 S2S2

12. Spring 2006 12 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering MUX Implementation 0 1 2 3 Q0 Q1 0 IN1·IN0 S 0 1 2 3 Din Q1,Q0 IN1·IN0 Gnd IN1·IN0 LS153 2

13. Spring 2006 13 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering Find the reduced K-map? 0 132 4 576 8 9BA C DFE Q1 Q0 IN1 IN0 00 011110 00 01 11 10 0 10 0 1 1 01 1 1 1 0 001 1 S0S0 S1S1 S3S3 S2S2

14. Spring 2006 14 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering Find the Implementation? 0 1 2 3 Q0 Q1 S 0 1 2 3 Din Q1,Q0 LS153 2

15. Spring 2006 15 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering NSD ROM implementation ROM replaces combinational logic Implementation –K-map inputs and present state connect to address lines –Outputs drive D inputs –ROM is programmed with data (text file for B2Logic)

16. Spring 2006 16 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering ROM Example 0 132 4 576 8 9BA C DFE Q1 Q0 IN1 IN0 00 011110 00 01 11 10 1 11 0 0 0 00 0 0 0 0 000 0

17. Spring 2006 17 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering ROM Implementation 16 x 1 ROM A0A0 A1A1 A2A2 A3A3 D0D0 Q0 Q1 IN0 IN1 D0 Connect present state to upper address lines

18. Spring 2006 18 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering ROM text file AddressData 01 71 61 NOTE: ROM text files default to zero

19. Spring 2006 19 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering Find the ROM text file? 0 132 4 576 8 9BA C DFE Q1 Q0 IN1 IN0 00 011110 00 01 11 10 0 10 0 1 1 01 1 1 1 0 001 1

20. Spring 2006 20 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering ROM text file? AddressData

21. Spring 2006 21 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering What is a bus? ··· Signal 0 Signal n Agent 0 Agent n ··· Bus Bus: collection of n parallel signals

22. Spring 2006 22 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering Example Buses? USB PCI, PCI-E AGP ISA, EISA ATA, SATA SCSI MULTIBUS, VERSABUS, DECBUS

23. Spring 2006 23 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering Bus properties Agents –Master: owns bus –Slave: responds to requests Interconnections –Parallel, serial –Point-to-point, distributed –Single- and multi-master

24. Spring 2006 24 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering Bus properties, continued. Electrical –Synchronous, asynchronous –Logic families: setup, hold, propagation –Impedance, length, speed Performance –Bandwidth, B/s –Turn-around time, t

25. Spring 2006 25 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering Bus signal groups Address –Identifies memory location –Identifies I/O port number Data –Contains information –Uni- or Bi-directional (tri-state) Control: coordinates actions

26. Spring 2006 26 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering Example bus control signals? Clock, reset Read, write Memory, I/O operation Interrupt request, interrupt acknowldge Bus request, Bus grant Slow down (wait)

27. Spring 2006 27 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering Bus cycle (phases) 1.Arbitration: owner defined 2.Address: ID of memory or I/O provided 3.Data: information transferred 4.Response: indicates completion of cycle

28. Spring 2006 28 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering Class CPU model Goals –Provide CPU model for use with B2Logic simulator –Offer simple bus structure: control, address, data –Support multiple processors Inputs: reset, clock, ack, busgnt, int Outputs: control, address, data, busreq, inta

29. Spring 2006 29 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering CPU functional diagram CPU Model Reset/ Clk Ack Busgnt Int C A D Busreq Inta

30. Spring 2006 30 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering Inputs Reset/ Places CPU in known state Clk Clock for synchronous logic Ack Indicates bus cycle complete Busgnt Bus granted to CPU Int Interrupt request

31. Spring 2006 31 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering Outputs A Address of bus operation (8 bits) D Data for bus operation, it is a bi-directional bus (8 bits) C Control bits indicate type of bus operation (4 bits) Busreq CPU requests use of bus Inta CPU acknowledges an interrupt input

32. Spring 2006 32 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering CPU block diagram PCROM FSM Tri-State Buffer Breq Inta Bgnt Ack Int CADCAD Note: no data read into CPU

33. Spring 2006 33 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering CPU schematic Next project

34. Spring 2006 34 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering

35. Spring 2006 35 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering Find the Implementation ? 0 1 2 3 Q0 Q1 IN0 S 0 1 2 3 Din Q1,Q0 LS153 IN1·IN0 1 IN0 IN1·IN0 IN0 1 2

36. Spring 2006 36 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering ROM text file? AddressData 11 31 71 81 a1 c1 d1 e1 f1

37. Spring 2006 37 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering Example Buses? PCI: peripheral component interchange SCSI: small computer system interchange AGP: accelerated graphics port USB: universal serial bus HIPPI: high performance parallel interface IEEE 1394 (Fire Wire): faster USB

38. Spring 2006 38 EE 437 Lillevik 437s06-l2 University of Portland School of Engineering Example bus control signals? Bus request, grant Read, write Memory, I/O space Address, data valid Wait Interrupt request, acknowledge