1. SVX4 chip 4 SVX4 chips hybrid 4 chips hybridSilicon sensors Front side Back side Hybrid data with calibration charge injection for some channels IEEE Nuclear Science Symposium 2003, Portland, Oregon, U.S.A. Oct. 19-25, 2003 CDF Run IIb Silicon : Stave design and testing Rong-Shyang Lu, Academia Sinica, Taiwan Hybrid electronics Foam core Peek Cooling channels 2.9 x 5.6 mm Silicon Sensors 4mm separation Stave Elements 1 module = 2 silicon sensors wire bonded and readout by 1 hybrid with 4 SVX4 chips 3 modules per side bus cable between silicon and stave core 1 Mini Port-card per stave 1 readout unit per stave (3072 channels) Mechanical Overview 66 cm long Carbon fiber composite skins on a foam core Build-in cooling tube (PEEK) Kapton bus cables for data and power distribution 6 silicon sensors glued on top of bus cables, one per side Hybrids glued and wire bonded on silicon Readout chips bounded down to bus cable Mechanical Support Stave position is registered by pins in two end The mass of stave results in a sag of 150  m which is within 160  m specification Finite element analysis of stave structure under gravity Stave Cooling Need to operate from -5 C (inner) to 15 C (outer) 18.3 W heat generated by stave Build-in U-shaped cooling tube 0.1 mm wall radiation tolerant polyethylethylketone (PEEK) plastic tube Assume coolant temp of -15 C, the highest temperature spot is 0 on stave 43% ethylene glycol by weight in water for operation at -15 C Stave temperature distribution Heat Load per stave (W) SVX4 chips (24)9.6 Convection4.2 Mini Port-card2.5 Leakage current (6 cm)1.6 Total per stave (W)18.3 Total Layers 2-5 (W)3240 Stave Readout Electronics SVX4 chip  0.25  m CMOS technology  128 parallel charge integration channels  low resistivity substrate exploited for ground distribution and digital/analog isolation  128 ADC with real time pedestal subtraction Hybrid  BeO substrate for low mass and good thermal conductivity  4 gold layers and 100/100  m trace/space and 125  m vias  service 4 SVX4 chips to connect to Mini Port- card. Mini Port-card  BeO substrate as hybrids  wing cable connect top and bottom bus cable  5 transceiver chips for bidirectional data control Stave Material 1.8% radiation length (X 0 ) for one stave Smooth material distributions For whole detector, expect 6% X 0 from silicon, carbon fiber and cooling structure; 12% X 0 due to additional readout hybrids. Single element from 2 nd to 6 th layers  reduce component count  reduce fixturing  faster construction Radiation hard SVX4 readout chips Low mass, redistribute material optimally Highly integrated electrical, mechanical, and thermal structure.  active cooling  embedded signal and power distribution network  6 modules mounted on stave (3 on each side) BeO Mini Port-card Stave Electrical Testing Pedestal and noise / differential noise (dnoise, i.e. common mode noise suppressed) Dnoise around 1100 electrons (e - ) (depending on setting) Noise coincide with dnoise which is essential for sparse readout operation Minimum Ionizing Particle (MIP) signal 22,000 e - (S/N ~ 20) Best performance when  Al shielding between Si and bus cable properly grounded  HV bias return to AGND  Al box ground to AGND @ PS Full stave pedestal distribution Full stave noise / dnoise distribution Stave Schedule and Plan Will build 15 staves in the end of 2003 Sensors are ready; hybrids and Mini Port-cards are in production. At least 5 staves assembled in barrel with some Layer0 modules Read out multiple staves and study performance Laser signal with Offline Pedestal Subtraction Stave Data of Laser Run Shine laser light on silicon of a stave Clear and clean laser signal after pedestal subtraction Chip/Hybrid/Module Testing Study the performance of all chips / hybrids / modules Test the components and perform burn-in before module / stave assembling. Pedestal vs channels for SVX4 chip SVXIIb Detector Barrel Layout Side view Layer 0: 12 fold Axial Layer 1: 6 fold Axial-Axial Layer 2: 12 fold Axial-SAS(1.2  ) Layer 3: 18 fold SAS(1.2  )-Axial Layer 4: 24 fold SAS(1.2  )-Axial Layer 5: 30 fold Axial-Axial Sensors Hybrids Stave Design Single-sided silicon sensor  320  m thickness and 75  m pitch for Axial (80  m stereo)  depletion voltage >100V and <200V Hybrids and Mini Port-card used to readout signal Complies with deadtime-less operation of readout electronics A module = 1 hybrid + 2 Si 1,100 e - noise Bow-shaped problem corrected on the new SVX4 chip version Optimized chip setting Noise vs channels for SVX4 chip Capacitance load Noise vs channels for SVX4 chip 0 pF 10 pF 20 pF