1. Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 2-3

2. Abstract Today’s class:  Modules:  Program structure  Lexical tokens  Data types  Modulation instantiations  Examples 2

3. Modules The Verilog language describes a digital system as a set of modules. Each of these modules has an interface (port) to other modules to describe how they are interconnected. The top level module invokes instances of other submodules where may run concurrently. The top module specifies a closed system containing both test data and hardware models. 3

4. Modules The structure of a module is the following: module ( ); ; endmodule – Module name: an identifier uniquely names the module – Port list: a list of input and output ports used to connect to other modules – Declares: specify data objects as registers, memories, wires and procedure constructs – Module items: initial, always constructs, continuous assignment or instances of modules. 4

5. Program Structure- Lexical Tokens( 語詞的標記 ) White Space: –space –tab –newline Comments: – // (one line commented); – /* and */ (more than one line are commented) Numbers: – Storage is defined as a number of bits. E.g. reg [31:0] a,b,c: declare a, b, and c as 32-bit variables – Values are specified in binary, octal, decimal, hexadecimal. E.g. 3’b001 (binary), 5’d30(=5’b11110) (decimal), 16’h5ED4(=16’d24276) (hexadecimal) 5

6. Program Structure- Lexical Tokens Identifiers: – User defined words for variables, function names, module names, block names, and instance names. –Simple identifier: [a-zA-Z][a-zA-Z_$] –Escaped identifier: \{Any_ASCII_character_except_white_space} –Examples:  _ok,ok_,OK_$,Ok_123,CASE_SENSITIVE,case_sensitive  \ok, \/ok, Operators: – Consisted of one, two and sometimes three characters used to perform operations on variables. – E.g. >, +, ~, &, != 6

7. Program Structure- Data Types Keywords: – Specially reserved words that are part of the Verilog language. – A list of keywords is shown in Table 2-2. They should not be used as identifiers. Logic values: ‘0’, ‘1’, ‘x’, ‘z’ –‘0’: logic zero or false condition. –‘1’: logic one or true condition. –‘x’: uninitialized or unknown logic value –‘z’: high-impedance state Registers –Command: reg –The reg variables are data objects that store the last value which was procedurally assigned to them.  They are used only in functions and procedural blocks (e.g. initial, always).  In multi-bit registers, data is stored as unsigned number of vector. 7

8. 8 always and assign attribute begin buf bufif0 bufif1 case casex casez cmos deassign default defparam disable endattrib ute endcase edge else end endfuncti on endmodul e endprimiti ve endspecif y endtable endtask event for force forever fork function ifnone initial inout highz0 highz1 if input integer join medium module large macromo dule nand negedge nmos nor not output parameter pmos notif0 notif1 or posedge primitive pull0 pull1 pulldown pullup rcmos real realtime reg release repeat rtranif1 scalared signed rpmos rtran rtranif0 small specify specpara m strength strong0 strong1 supply0 supply1 table task time tran tri0 tri1 triand tranif0 tranif1 tri trior trireg unsign ed vectore d wait wand weak0 weak1 while wire wor xnor xo r Verilog HDL Keywords

9. Program Structure- Data Types Syntax of register: –reg [msb:lsb] register variable list; –msb: maxi. significant bit –lsb: least significant bit Example: –reg a; // single 1-bit register variable –reg [7:0] tom; // an 8-bit vector; a bank of 8 registers –reg [5:0] b,c; // two 6-bit variables b and c Examples: monitest.v, counter.v (chapter 2) 9

10. Program Structure- Data Types Nets: wire, wand, wor, tri –Wire:  A physical wire in a circuit and is used to connect gates or modules.  Unable to store its value and must be driven by a continuous assignment (assign) statement or by connecting it to the output of a gate or module.  A single-bit wire is a scalar. We may also declare a wire as a vector. –Other types of wires:  wand (wire-AND): depending on logic AND of all the drivers connected to it.  wor (wire-OR): depending on logic OR of all the drivers connected to it.  tri (three-state): all drivers connected to tri must be z. –Syntax: wire [msl:lsb] wire variable list 10

11. Program Structure- Data Types Input, output, input-output ports: – Command: input, output, inout –Declare input, output and bi-directional ports of a module or task. –An input or output port can be configured to be of type wire, reg, wand, wor or tri. The default is wire. –Syntax:  input [msb:lsb] input_port_list; declare input port  output [msb:lsb] output_port_list; declare output port  inout [msb:lsb] inout_port_list; // declare tri-state bus –Example (chapter 3):  dff.v, mux2_1.v, dff_sel.v  wand_example.v, wor_example.v  NAND.v  triBuffer.v, wire_types.v 11

12. 12 D-type Flip-Flop 2-1 multiplexer Selective output data

13. 13 Selective output data

14. Wire-And 14

15. Wire-Or 15

16. in1in2ANDNADN 1110 1001 0101 0001 Not-And 16

17. Tri-state 17

18. Wire-Types 18

19. Program Structure- Data Types Integer: –Command: integer –General purpose variables and store data as signed number (positive/negative), which defaults to 32-bit, range: [2^31-1,-2^31] –Example:  integer a; // single 32-bit signed integer initial a=-5; Real: –Command: real –64 bits long using decimal (1000.00) or scientific notation (1.0e3), range: [2^63-1,-2^-63] –Example: –real alpha; // single 64-bit real initial alpha=1.3e10; 19

20. Program Structure- Data Types Time: –Command: time –64 bits reg varialbe to get the present simulation time. –Example: reg [63:0] current_time = $time; // declare and initialize variable Parameter: –Command: parameter –A constant that can be set when instantiating a module. –Example: (also see module parameterization) parameter wordsize=16; // define parameter wordsize reg [wordsize-1:0] data; // declare a vector data parameter a=16, b=-5, c=(a+b)/2; // define parameters 20

21. Program Structure- Data Types Array –Data type of reg, integer and time can be declared as array –Syntax: –Example:  reg a[7:0]; // declare 8 1-bit register variables: a[0],…,[7]. a is an array variable.  integer [7:0] b[15:0];// declare 16 8-bit (vector) integers: b[0],…b[15]. b is an array integer  reg[7:0] mem256[255:0]; // declare variable mem_256 as a register array variable having 8-bit of 256 elements. 21

22. Program Structure- Module Instantiations Module instantiations: module templates from which one creates actual objects (instantiations). Modules are instantiated inside other modules, and each instantiation creates a unique object from the template. The top-level module is its own instantiation. The instantiated module’s ports must match to those defined in the template by the following two approaches:  By port’s position: placing the ports in exactly the same positions in the port lists of both the template and the instance.  By port’s name: using a dot(.), in this case no need to follow the same position in the port lists of template “.template_port_name(name_of_wire_connected_to_port)” 22

23. Program Structure- Module Instantiations Syntax: –module_name instance_name_1(port_connection_list),..., instance_name_N(port_connection_list); Example: (chapter 3) –wire [3:0] in1,in2,o1,o2; and4 C1(in1,in2,01); // C1 ports referenced by position and4 C2(.a(in1),.b(in2),.c(o2));// C2 ports are referenced by name // where the template module definition: module and4(a,b,c); input [3:0] a,b; output[3:0] c; assign c= (a & b); endmodule –wire_types.v, diff_sel.v (chapter 3) 23

24. D-type Flip Flop 24

25. Program Structure – Parameterized Modules Module parameterization: Modules are parameterized by specifying the value of the parameter at each instantiation of the module. Syntax: – module_name #(parameter_values) instance_name(port_connection_list); Example: (chapter 3) – Shift_n.v – Test_shift.v 25

26. Test-Shift 26