1. Computer System Configuration and Function Computer Architecture and Design Lecture 6

2. Youpyo Hong & Kangwoo Lee @ DGU Micro-operation Digital Modules are best defined by  Registers  Operations performed on the data stored in them This “operation” is called the “micro-operation” Microoperation (  -op)  An elementary operation performed on data stored in register(s)  Results of operations may Replace previous data, or Be transferred to another register  Example: Shift, Count, Clear, Load, Add, Sub,... 2

3. Youpyo Hong & Kangwoo Lee @ DGU Definition of RTL Hardware Organization is Best Defined by specifying  Set of registers in it & their functions  Sequence of  -ops performed on data stored in registers  Controls governing the execution of  -ops RTL (Register Transfer Language)  Definition: Symbolic notation describing data xfers &  -ops between registers  Usefulness:  -ops imply the availability of hardware logic circuits that can perform specified  -ops RTL can be transformed to hardware by tools 3

4. Youpyo Hong & Kangwoo Lee @ DGU  -operations that we will learn Register Transfer Bus & Memory Transfer Arithmetic  -ops Logic  -ops Shift  -ops Arithmetic Logic Shift Unit (ALU) 4

5. Youpyo Hong & Kangwoo Lee @ DGU Registers Notation: Capital letters (for naming) + optional numerals 5 NameDescriptionUsage ARAddress RegisterTo designate memory location PCProgram CounterTo designate next instruction IRInstruction RegisterTo store the instr. to execute DRData RegisterTo store operands / results R1General RegisterTo store temporary data 7 6 5 4 3 2 1 0R1 15 0 PC(H) 15 8 7 0 PC(L)

6. Youpyo Hong & Kangwoo Lee @ DGU Register Transfer Example: R2  R1 6  There are at least two registers (R1 & R2) in the system  There is a connected path between R1 & R2 for data movement  R2 has “parallel load” function  There are at least two registers (R1 & R2) in the system  There is a connected path between R1 & R2 for data movement  R2 has “parallel load” function  Transfer of the content in R1 into R2  Content of R1 does not change  Transfer of the content in R1 into R2  Content of R1 does not change Hardware Operation

7. Youpyo Hong & Kangwoo Lee @ DGU Control Function 7  Goal: To let operations take place under a certain condition  Example: P: R2  R1 Register xfer from R1 to R2 is done only when P=1 Control Circuit R2 R1 clock Load P n P is set to 1Xfer occurs tt+1

8. Youpyo Hong & Kangwoo Lee @ DGU Basic Xfer Operations 8 Symbol Letters (+ Num) Parenthesis Arrow Comma Description Denotes register Denotes part of a register Denotes information xfer Separate simultaneous  -ops Examples R1, AR, PC R1(0-7), R2(L) R2  R1 R2  R1, R1  R2

9. Youpyo Hong & Kangwoo Lee @ DGU Common Bus Bus : Set of wires, one for each bit, thru which binary data are xferred Common Bus  Paths must exist to xfer data among many registers  Control Signal determines registers for data movement BUS  C, R1  BUS  R1  C 9 Register Register-to-Register ConnectionCommon Bus-based Connection

10. Youpyo Hong & Kangwoo Lee @ DGU Common Bus Control Sender Side  MUX selects the sender Receiver Side  Load signal is selected 10 R1 R2 IR DR N R x 1 MUX Control Unit Select Load Common Bus

11. Youpyo Hong & Kangwoo Lee @ DGU Bus System for Registers 11 4x1 MUX 3 2 1 0 D 2 C 2 B 2 A 2 4x1 MUX 3 2 1 0 D 1 C 1 B 1 A 1 4x1 MUX 3 2 1 0 D 0 C 0 B 0 A 0 4x1 MUX 3 2 1 0 D 2 D 1 D 0 3 2 1 0 C 2 C 1 C 0 3 2 1 0 B 2 B 1 B 0 3 2 1 0 A 2 A 1 A 0 S1S0S1S0 Register DRegister CRegister BRegister A 4 line common bus

12. Youpyo Hong & Kangwoo Lee @ DGU Three-State Bus Buffers 3-State Gates  Output : 0, 1 & High Impedance  Buffer gate is the most popular Bus line with 3-state buffers 12 2x4 Dec. Bus line for bit 0 A0B0C0D0A0B0C0D0 S1S0S1S0 Enable Select E 01230123 Input A Cmtr C Output: Y = A if C=1 H.I. If C = 0

13. Youpyo Hong & Kangwoo Lee @ DGU Memory Transfer Need to specify memory location of interested data Example: Read: DR  M[AR] Write: M[AR]  DR 13

14. Youpyo Hong & Kangwoo Lee @ DGU Arithmetic Microoperations 14  Basic Arithmetic  -ops : +, -, Increment, Decrement & Shift  Example: R3  R1 + R2  There are at least three registers (R1, R2, R3)  There are connected paths among R1, R2 & R3  There is an functional unit that can perform arithmetic addition  R3 has “parallel load” function  There are at least three registers (R1, R2, R3)  There are connected paths among R1, R2 & R3  There is an functional unit that can perform arithmetic addition  R3 has “parallel load” function  Perform addition of the contents stored in R1 and R2  Transfer of the result into R3  Contents of R1 & R2 do not change  Perform addition of the contents stored in R1 and R2  Transfer of the result into R3  Contents of R1 & R2 do not change Hardware Operation

15. Youpyo Hong & Kangwoo Lee @ DGU Basic Arithmetic  -ops 15 Contents of R1 plus R2 xferred to R3 Contents of R1 minus R2 xferred to R3 Complement contents of R2 (1’s complement) 2’s complement of R2 (negate) Description R3  R1 + R2 R3  R1 - R2 R2  R2’ R2  R2’ + 1 Symbol R1 plus 2’s complement of R2 (subtraction) Increment content of R1 by 1 Decrement content of R1 by 1 R3  R1 + R2’ + 1 R1  R1 + 1 R1  R1 - 1

16. Youpyo Hong & Kangwoo Lee @ DGU Binary Adder 16 FA C4C4 B3B3 A3A3 S3S3 C3C3 B2B2 A2A2 S2S2 C2C2 B1B1 A1A1 S1S1 C1C1 B0B0 A0A0 S0S0 C0C0 x S C y z Full Adder

17. Youpyo Hong & Kangwoo Lee @ DGU Binary Adder-Subtractor 17 FA C4C4 B3B3 A3A3 S3S3 C3C3 B2B2 A2A2 S2S2 C2C2 B1B1 A1A1 S1S1 C1C1 B0B0 A0A0 S0S0 C0C0 M If M = 0  A + B If M = 1  A + (B’ + 1)  A - B

18. Youpyo Hong & Kangwoo Lee @ DGU Arithmetic Circuit 18 4x1 MUX S1S00123S1S00123 X 1 C 1 FA Y 1 C 2 D1D1 A1A1 B1B1 4x1 MUX S1S00123S1S00123 X 2 C 2 FA Y 2 C 3 D2D2 A1A1 B1B1 4x1 MUX S1S00123S1S00123 X 0 C 0 FA Y 0 C 1 D0D0 A1A1 B1B1 4x1 MUX S1S00123S1S00123 X 3 C 3 FA Y 3 C 4 D3D3 A1A1 B1B1 C out C in S 1, 0 0 0 0 0 BD = A + BAdd0 0 1 BD = A + B + 1Add w/ carry0 1 0 B’D = A + B’Sub w/ barrow0 1 1 B’D = A + B’+ 1Sub1 0 0 0D = AXfer A1 0 D = A + 1Inc. A1 1 0 1D = A - 1Dec. A1 1 D = AXfer A S 0 S 1 C in Y Output D=A+Y+C in  -ops Select

19. Youpyo Hong & Kangwoo Lee @ DGU Logical Microoperation Binary operations for strings of bits stored in registers. Example1: P: R1  R1  R2 Example2: Mixed use of Operators 19 1010 Content of R1 1100 Content of R2 0110 Content of R1 when P=1 P + Q: R1  R1 + R2, R3  R4  R5 OR Operation Add Operation OR Operation

20. Youpyo Hong & Kangwoo Lee @ DGU H/W Implementation of Some Logic  -ops 20 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 F  0Clear AND Transfer A Transfer B EX-OR OR NOR EX-NOR Comple. B Comple. A NAND Set to all 1’s F0F0 F1F1 F2F2 F3F3 F4F4 F5F5 F6F6 F7F7 F8F8 F9F9 F 10 F 11 F 12 F 13 F 14 F 15  -ops Name All possible functions for two variables Boolean Function F 0 = 0 F 1 = xy F 2 = xy’ F 3 = x F 4 = x’y F 5 = y F 6 = x  y F 7 = x + y F 8 = (x + y)’ F 9 = (x  y)’ F 10 = y’ F 11 = x + y’ F 12 = x’ F 13 = x’ + y F 14 = (xy)’ F 15 = 1 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 F  A  B F  A  B’ F  A F  A’  B F  B F  A  B F  A  B F  (A  B)’ F  (A  B)’ F  B’ F  A  B’ F  A’ F  A’  B F  (A  B)’ F  all 1’s

21. Youpyo Hong & Kangwoo Lee @ DGU H/W Implementation of Some Logic  -ops AND, OR, XOR & Complement, only 21 AiAi BiBi S1S1 S0S0 EiEi 4 x 1 MUX 0 1 2 3 Comple. A11 E  A’ EX-OR10 E  A  B OR01 E  A  B AND00 E  A  B OperationS1S1 S0S0 Output

22. Youpyo Hong & Kangwoo Lee @ DGU Shift Operation – Logical Shift 22 R1  shl R1 01101 110100 Serial Input Lost R1  shr R1 01101 001101 Serial Input Lost

23. Youpyo Hong & Kangwoo Lee @ DGU Shift Operation – Circular Shift 23 R1  cil R1 01101 11010 R1  cir R1 01101 10110

24. Youpyo Hong & Kangwoo Lee @ DGU Shift Operation – Arithmetic Shift 24 R1  ashr R1 01101 001101 SignLost 11101 111101 SignLost Complemented form of zero zero  Divide by 2  Keep the sign bit  MSB of Mag. is Zero, always NOTE:

25. Youpyo Hong & Kangwoo Lee @ DGU R1  ashl R1 00101 010100 Serial Input Lost Sign 11001 100101 Serial Input Lost Sign Complemented form of zero Actually, insert Zero at MSB position 0 1101 1 10100 Serial Input Lost Sign 1 0001 0 00100 Serial Input Lost Sign Complemented form of one Change of Sign bit  Overflow Overflow Condition: V s = R n-1  R n-2 25

26. Youpyo Hong & Kangwoo Lee @ DGU H/W Implementation of Shift  -ops 26 MUX S01S01 H0H0 S01S01 H1H1 S01S01 H2H2 S01S01 H3H3 A0A0 A1A1 A2A2 A3A3 Select: 0 shift right (down) 1 shift left (up) Serial Input

27. Youpyo Hong & Kangwoo Lee @ DGU Arithmetic Logic Unit with Shift  -ops 27 One stage of arithmetic circuit (Fig. 4.9) One stage of logic circuit (Fig. 4.10) 4 x 1 MUX S0123S0123 S3S3 S2S2 S1S1 S0S0 BiBi AiAi B i-1 A i-1 shl EiEi DiDi FiFi CiCi C i+1 shr 14  -ops in all 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 x 0 1 0 1 x 0 1 1 0 x 0 1 1 1 x 1 0 x x x 1 1 x x x S 3 S 1 C in S 2 S 0 F  A Inc. Add Add w/ carry Sub w/ borrow Sub Dec.  -ops Name F  A+1 F  A+B F  A+B+1 F  A+B’ F  A+B’+1 F  A-1 F  A F  A  B F  A  B F  A  B F  A’ F  shr A F  shl A