1. Hans Henschel 12-Feb-06FCAL Meeting Cracov 1 FLC-PHY3 Frontend Chip Channels18 Gain values16 (adjustable - 300mv/pC … 5V/pC) 1:1, 1:10 (dynamically selectable per channel) Track & Holdwith sequential readout (shift register) - rate?? Packaging64pin TQFP Peaking Time~200ns Gain uniformity between channels3% Linearity0.3…1.6% Noise100µV + 1.7µV/pF (Gain 1) 500µV + 17µV/pF (Gain 10) Crosstalk0.1% Main Parameters

2. Hans Henschel 12-Feb-06FCAL Meeting Cracov 2 PHY3 Prototyping Frontend Board 6 (+ 4) sensors (36 channels each) 12 frontend chips (18 channels) FLC-PHY3 36 passive components per f/e chip (biasing) 2 dedicated calibration chips, driving 12 LEDs ("no spares available") remote connector with - 12 serialized analog outputs - 5 digital differential controls (shift register) - several calibration controls Features

3. Hans Henschel 12-Feb-06FCAL Meeting Cracov 3 Future Development Power Cycling (tested on prototypes) ADC (10…12 bit) elimination of external passive components calibration circuitry on chip sparsification?