1. Microarchitecture of Superscalars (5) Dynamic Instruction Issue Dezső Sima Fall 2007 (Ver. 2.0)  Dezső Sima, 2007

2. Overview 1 The principle of dynamic instruction issue 2 Design space 5 Case examples 2.1 Overview 2.2 Types of issue buffers 2.3 Operand fetch policies 4 Implementation of dynamic instruction issue in superscalars 4.1 The introduction of dynamic instruction issue 4.2 Basic implementation schemes 3 Principle of operation of dynamic instruction issue 3.1 Dispatch bound operand fetching 3.2 Issue bound operand fetching

3. 1. Principle of dynamic instruction issue (1) Aim: To eliminate the issue bottleneck of early (first generation) supercalars

4. 1. Principle of dynamic instruction issue (2) The issue bottleneck (b): The issue process(a): Simplified structure of the mikroarchitecture assuming unbuffered issue Figure 1.1: The principle of dynamic instruction issue Icache I-buffer Instr. window (3) Decode, check, issue Dependent instructions block instruction issue EU Issue EU

5. 1. Principle of dynamic instruction issue (3) Figure 1.2: Principle of dynamic instruction issue (b): The issue process(a): Simplified structure of the mikroarchitecture assuming buffered issue (shelving) Eliminating the issue bottleneck Dynamic instruction issue (shelving, buffered issue)

6. Layout of the issue buffers Scope of dynamic instr. issue Instruction issue scheme Dynamic instruction issue Operand fetch policy 2. Design space of dynamic instruction issue 2.1 Overview Types of issue buffers

7. 2.2 Types of issue buffers Reservation stations (RS) Issue buffers in the ROB Types of issue buffers Individual RSs Central RS Group RSs RS FX EU RS FP EU FX EU RS FP EU FX EU FP EU Power1 (1990) PowerPC 603 (1993) PowerPC 604 (1995) Power4 (2001) Power5 (2004) K5 (1995) K7 (1999), K8 (2003) RS FX EU FX EU RS FX EU FP FX EU ES/9000 (1992) Power2 (1993) R10000 (1996) PM1(Sparc64)(1995) Alpha 21264 (1997) Pentium Pro (1995) Pentium II (1997) Pentium III (1999) Pentium IV (2000) Pentium M (2003) Core (2006) Lightning (1991)p K6 (1997)

8. Layout of the issue buffers Scope of buffered issue Instruction issue scheme Dynamic instruction issue Operand fetch policy Types of issue buffers

9. 2.3 Operand fetch policies Dispatch bound operand fetch policy Issue bound operand fetch policy Operand fetch policies Decode / Issue EU Reg. file IB OCRdOp1/Rs1Op2/Rs2OC I-buffer Source reg. identifiers Opcodes, destination reg. identifiers Source 1 operands Source 2 operands EU Rd, result IB Rd Op1/Rs1 Op2/Rs2 I-buffer Source reg. identifiers Opcodes, destination reg. identifiers Source 1 operands Source 2 operands OCRd IB OCRd Decode / Issue Reg. file EU Source reg. identifiers Rs1Rs2 IB Rs1Rs2 Dispatch Issue Dispatch Issue Figure 2.1: Operand fetch policies

10. 3 Principle of operation of dynamic instruction issue 3.1 Dispatch bound operand fetching (1) Checking the availability of operands Decode / Issue EU Reg. file IB OCRdOp1/Rs1Op2/Rs2OC I-buffer Source reg. identifiers Opcodes, destination reg. identifiers Source 1 operands Source 2 operands EU Rd, result IB Rd Op1/Rs1 Op2/Rs2 Dispatch Issue V V V V V

11. 3.1 Dispatch bound operand fetching (2) Updating the issue buffers Decode / Issue EU Reg. file IB OCRdOp1/Rs1Op2/Rs2OC I-buffer Source reg. identifiers Opcodes, destination reg. identifiers Source 1 operands Source 2 operands EU Rd, result IB Rd Op1/Rs1 Op2/Rs2 Dispatch Issue V V V V V

12. 3.2 Issue bound operand fetching Checking the availability of operands I-buffer Source reg. identifiers Opcodes, destination reg. identifiers Source 1 operands Source 2 operands OCRd IB OCRd Decode / Issue Reg. file EU Source reg. identifiers Rs1Rs2 IB Rs1Rs2 Dispatch Issue V

13. 4. Implementation of dynamic instruction issue in superscalars 4.1 The introduction of dynamic instruction issue Figure 4.1: The introduction of dynamic instruction issue

14. Reservation stations (RS) Issue buffers in the ROB Basic issue buffer schemes Individual RSs Central RS Group RSs Types of issue buffers Operand fetch policy Dispatch bound Issue bound Dispatch bound Issue bound Dispatch bound Issue bound Dispatch bound Issue bound PowerPC 603 (1993) PowerPC 604 (1995) K5 (1995) Power1 (1990) Power4 (2001) Power5 (2004) Nx586 (1994) K7 (1999), K8 (2003) PM1(Sparc64) (1995) ES/9000 (1992) Power2 (1993) R10000 (1996) Alpha 21264 (1997) Pentium Pro (1995) Pentium II (1997) Pentium III (1999) Pentium IV (2000) Pentium M (2003) Core (2006) Lightning (1991)p K6 (1997) 4.2 Basic implementation schemes

15. 5. Case example (1) Individual issue buffers Figure 5.1: The microarchitecture of the Athlon

16. 5. Case example (1) Individual issue buffers (2) Figure 5.2: Integer issue buffers of the K8L Source: Malich, Y.„AMD's Next Generation Microarchitecture Preview: from K8 to K8L”, Aug. 2006. Issue buffers Decoders EUs

17. 5. Case example (2) Group issue buffers Figure 5.3: The microarchitecture of the Alpha 21264 Source: Kessler, R.E. et al..„The Alpha 21264 Microprocessor Architecture”, h18002.www1.hp.com/alphaserver

18. 5. Case example (3) Central reservation station (1) Figure 5.3: The microarchitecture of the Core processor Source: Kanter, D., „Intel’s next Generation Microarchitecture Unveiled”, Real World Tech., 2006 March 9.