1. Toshiba Understanding Costs of Chip Design and Manufacture Peter Hsu, Ph.D. Chief Architect Microprocessor Development Toshiba America Electronics Components, Inc. Created 22 February 2001 at the University of Wisconsin in Madison

2. Outline Manufacturing Cost Design Cost Pricing Big Picture Summary § The costs, prices and revenue models in this presentation are for illustration purposes only, and have no relationship to Toshiba.

3. Manufacturing Cost Functional Silicon Die –Die Size –Process Maturity Package & Assembly –Substrate vs. Lead Frame Frequency Yield –Production Volume

4. Yield as Function of Die Size

5. Functional Die Cost § Assumption: 200mm (8 inch) wafers at $3,000 each

6. Typical Parameters Defect Densities –New Process: 10 per inch 2 (1.5 per cm 2 ) –Volume Production: 5 / in 2 (0.8 / cm 2 ) –Mature Process: 2 / in 2 (0.3 / cm 2 ) Wafer Costs –Mature Process (e.g. 0.25µm): $2,000 –New Process (e.g. 0.15 µm): $5,000 § Estimated from diverse industry sources. Data is not representative of any particular fab or company. Wafer costs fluctuate and increases over time.

7. Packages Lead Frame –Cheap –Poor: Electrically Thermally Substrate –Moderate Cost –Good Performance Hermetically Sealed? Lead Frame Punched from Tape Encapsulation by Plastic Injection-Mold Cavity-Down Thermally Enhanced Plastic Ball Grid Array Typical Cost: $1 Typical Cost: $4

8. Example #1: Graphics Chip § Assumption: 200mm (8 inch) wafers at $3,000 each, defect density 0.8 Total: $16.31

9. Example #2: After Shrink § Assumption: 200mm (8 inch) wafers at $3,000 each, defect density 0.8 Total: $9.68

10. Process Variation

11. Example #3: Speed Sorted § Assumption: 200mm (8 inch) wafers at $3,000 each, defect density 0.8 Total: $18.62

12. Sanity Check: DRAM Defect Density –Higher: much denser fine geometry –Offset by redundancy Wafer Cost –More complex front end for capacitor –Offset by less metal layers (e.g. 1 W + 2 Al) 64Mbit in 0.25µm: $7 ?? –0.55 µm 2 cell, 65% cell area: 58mm 2 die –$2,000 wafer, 84%yield: $5 27 die –30¢ TSOP, $1 test/redundancy, 50¢ handling

13. Design Cost Time –How Long Until Revenue Resources –No. People, Experties, CAD Tools Risk –Schedule Slip –Performance Irregularities –Reliability Problems

14. Typical Project Schedule Architecture Logical Design (RTL) Logical Verification Physical Design (Synthesis, P&R) Physical Verification (Timing) Prototype Fabrication, Package Silicon Debug In-System Verification 2nd Physical Design 2nd Physical Verification Production Fabrication 9 months 12 month 9 month 6 month 3 2 4 3 3 9 months 1 st tapeout customer samples 2 nd tapeout Years 12.250.250.50.751.251.51.7522.52.753 Variations: Startup: Architecture –6 Big Company: System Verif. +6

15. Typical Manpower Requirements Performance Logical Design Logical Verification Physical Design Physical Verification Package Design Reference Board Design In-System Verification 2nd Physical Design 2nd Physical Verification Documentation 5 – 25 5 - 50 2 - 30 1 - 3 1 - 5 2 – 10 Quarters Range: Startup – Mature Company

16. Design Cost Summary $333K § per Person Year –Low: 20p x 3y = $20M –High: 150p x 3.5y = $175M Amortize –High Volume Demand Generation Derivative Products –High-Value System Product § Compensation $150K + 50% Benefits + 50% Equipment + 20% Facilities

17. Example #1: PC Graphics Chip § Highest volume PC OEM product line shipped several million in year 2000 Price: $46

18. Example #2: High-End Router § Chip revenue stream $100M. System revenue stream $1B? Price: $1,050

19. Return On Investment (ROI) #1: PC Graphics Chip $4M Profit  $20M  4yr = 5% Do better by investing in S&P 500 #2: High-End Router $14M Profit  $20M  4yr = 18% Can afford R&D for future Derivatives Help $16M Profit  $25M  7yr = 9%

20. Big Picture Business Models –Deep Pocket Demand Generation + Forward Pricing e.g. Nintendo, Sony Video Game Consoles Variant: Startup Company Acquisition –System Subsidy System Sales + Support Cost e.g. Sun Microsystem, Hewlett-Packard Microprocessors Variant: Subcontracted Design

21. Model #1: Deep Pocket Architecture Design Proto Fab (600mm 2 in 0.12µm) HW Debug/Qual Mass Production (400mm 2 in 0.10µm) Sales Channel 1st Shrink (300mm 2 in 0.09µm) 2nd Shrink (150mm 2 in 0.06µm) Software Development Promotion Campaign Year 20010602030405070809 0.18µm0.12µm0.09µm0.06µm 18 mo. 3 12 6 3 15 12 0.10µm demand 2010

22. Forward Pricing Process Generation Proto Fab (600mm 2 in 0.12µm) Mass Production (400mm 2 in 0.10µm) 1st Shrink (300mm 2 in 0.09µm) 2nd Shrink (150mm 2 in 0.06µm) Mature Process (0.06µm) Units Shipped Revenue, Price = $250 Net Gain: $1.8B ROI: ($1.8B – $175M)  $175M  9yr = 100% (– cost of $7.5B  2yr,...) Year 20010602030405070809 0.18µm0.12µm0.09µm0.06µm $1,900 $550 $50 $27 $250 0.10µm demand 2010 25M30M 15M ($7.5B)0$6B$3.3B

23. Model #2: System Subsidy Example: 16-Processor Server Price: $7,000 Cost: $6,000 Volume: 50,000 units  2 years NRE: Chip $20M + System $20M Recovery: $400 per system “Profit”: $600 per system ROI: $60M  $40M  5yr = 30% “A Better Server” Note System Sales + Support Cost » Chip Sales Cost

24. Summary Cost Implementation Architecture Marketing Sales Management Research Manufacturing Investment Profit The Business of Making Chips