1. 16/11/01GS/ALICE SPD/LHCC Referees1 ALICE Silicon Pixel Detector (SPD) G. Stefanini/CERN-EP General Front-end electronics – pixel bus – ALICE1 ASIC – PILOT ASIC, bias ASIC, optical link package, MCM Silicon sensors Beam test with bump-bonded assemblies Pixel wafer probing Pixel wafer thinning Mechanics and cooling Summary - Planning

2. 16/11/01GS/ALICE SPD/LHCC Referees 2 SPD (Hybrid Pixels) - Design Parameters Two barrel layers R i = 39mm, R o = 76mm Pixel cell dimensions50  m (r  ) x 425  m (z) Front-end electronics CMOS6 0.25  m standard process on 8” wafers, rad-hard design Pixel ASIC thickness (target)≤ 150  m (wafers thinned after bump deposition) Si sensor ladder thickness≤ 200  m Flip-chipsolder bumps/indium bumps Pixel busaluminium-polyimide flex Coolingwater/C 6 F 14 /[C 3 F 8 (evaporative)] Material budget (each layer)≈ 0.9% X 0 (Si ≈ 0.37, cooling ≈ 0.3, bus 0.17, support ≈ 0.1) Total Si surface≈ 0.24 m 2 Occupancy< 2%

3. 16/11/01GS/ALICE SPD/LHCC Referees 3 SPD Mechanical Configuration (I)

4. 16/11/01GS/ALICE SPD/LHCC Referees 4 SPD Mechanical Configuration (II) 2 barrel layers z= ± 14.15cm (sensitive) r1 = 3.9 cm, r2 = 7.6 cm

5. 16/11/01GS/ALICE SPD/LHCC Referees 5 SPD Ladders & Staves 1 sector one carbon-fibre support for layer 1+2 4 staves in outer layer 2 staves in inner layer ladder (1 sensor, 5 chips) half-stave: 2 ladders readout of 120 half-staves in parallel Image: INFN Padova SPD total 1200 pixel chips, ≈ 10 7 pixels

6. 16/11/01GS/ALICE SPD/LHCC Referees 6 Pixel Bus & Ladders (I) M. Morel ± 193 mm ladder1ladder2 70.72 mm Power supplies connector 1000mm Flexible Extender MCM Extenders (Copper-capton) Pixel bus: multilayer flex Al-polyimide So far, only satisfactory technology source is the EST PCB Workshop A-prototype (Cu) under test for signal integrity with 10 chips on bus B-prototype (Al) layout to start in Jan 02 (workload in EST layout section) Explore feasibility with industrial company

7. 16/11/01GS/ALICE SPD/LHCC Referees 7 Pixel Bus & Ladders (II) M. Morel

8. 16/11/01GS/ALICE SPD/LHCC Referees 8 End Stave Connections (I)

9. 16/11/01GS/ALICE SPD/LHCC Referees 9 ALICE Pixel ASIC CMOS6 0.25 µm (8” wafers) Radiation hard design (enclosed transistors) ≈ 13.10 6 transistors 8192 pixel cells 50 µm x 425 µm 256 rows, 32 columns Active area: 12.8mm x 13.6mm 10 MHz clock 1.8V power supply ~100 µW/channel M. Campbell

10. 16/11/01GS/ALICE SPD/LHCC Referees 10 Pixel Cell M. Campbell

11. 16/11/01GS/ALICE SPD/LHCC Referees 11 Pixel Chip JTAG Controls All configuration parameters are controlled through JTAG bus Two-fiber optical link, effective clock frequency 5 MHz Global registers –42 DACs for biasing –strobe delay –global threshold voltage –miscellaneous control (leakage current compensation, delay unit) Local registers (for each pixel cell): –3 bit threshold adjustment –TEST Enable –Pixel mask

12. 16/11/01GS/ALICE SPD/LHCC Referees 12 Test Set-Up VME Master R/O Controller Pixel Chip Carrier DAQ Adapter Pixel Chip P. Chochula JTAG Controller DAQLabView AnalysisROOT Database MySQL

13. 16/11/01GS/ALICE SPD/LHCC Referees 13 Radiation Test - Single Event Upsets (SEU) SEGR (Gate Rupture)  breakdown of transistor gate SEL (Latch-up)  high power supply current SEU (Upset)  switch logical level Alice1LHCb: 8192 Pixels: 5 memory cells each (3 threshold adjust, 1 mask, 1 test) 42 DACs:8 memory cells each (8 bit DACs) Hadrons may interact elastically and inelastically with Si atoms  recoils and fragments deposit a large amount of charge in the chip  Single Event Effect Mitigation: all critical memory cells are hardened by built-in redundancy J. Van Hunen

14. 16/11/01GS/ALICE SPD/LHCC Referees 14 SEU Cross Section (I) Measure SEU cross-section as function of the Linear Energy Transfer (LET) - at Louvain cyclotron (ions and protons) The LET is measured first with heavy ions Xe 26+, Kr 17+, etc., under different angles of incidence to cover the required range. J. Van Hunen

15. 16/11/01GS/ALICE SPD/LHCC Referees 15 SEU Cross Section (II) For the ALICE pixel detector: 1200 chips, 336 DAC bits  0.1 bit/hour Measurement with 60 MeV protons: The heavy ion results are used to calculate the SEU cross section for exposure to protons (60 MeV) :  9 10 -16 cm 2 per memory cell J. Van Hunen

16. 16/11/01GS/ALICE SPD/LHCC Referees 16 Pixel Chip Testing Four identical test setups have been installed in the CERN lab. Test of all internal DACs Threshold and noise scans Minimum threshold Current consumption Tests of the individual stages Functionality of the JTAG Used also for SEU measurements

17. 16/11/01GS/ALICE SPD/LHCC Referees 17 Bare Chip Threshold Scan Pulse each row (e.g. 250 triggers) with test-pulse (e.g. 0- 50 mV). Mean threshold: ~14-15mV RMS ~3mV. No individual threshold adjust. Conversion factor: ~66e - /mV (preliminary!) ~1000 e - mean threshold ~ 200 e - RMS P. Riedler

18. 16/11/01GS/ALICE SPD/LHCC Referees 18 Bare Chip Threshold Scan (II) Mean threshold vs. global threshold setting 3811 295121111288463Electrons RMS

19. 16/11/01GS/ALICE SPD/LHCC Referees 19 Bare Chip Noise Scan Determined from S-curve. Mean noise ~1.7-2 mV RMS ~ 0.2 mV Mean noise ~110 e - RMS P. Riedler

20. 16/11/01GS/ALICE SPD/LHCC Referees 20 Test Pulse Threshold map measured on chip 52 scale in mV pulser located under column 5 P. Riedler

21. 16/11/01GS/ALICE SPD/LHCC Referees 21 Fast Multiplicity for Trigger Fast Multiplicity: prompt analog output from each chip Half-stave sum ==> multiplicity in left and right part of barrel (Ml, Mr) Ml+Mr ==> total on SPD barrel ==> trigger on centrality Ml-Mr ==> left-right asymmetry ==> trigger on position of primary vertex (  ≈ few mm) Implementation study under way –analog optical signal transmission –contribution to L0 ? ( <1  s latency) Constraints on performance at very low multiplicity

22. 16/11/01GS/ALICE SPD/LHCC Referees 22 Engineering & Pre-production Wafers All tests so far with 6 engineering run wafers Some imperfections in design, but performance of the chip “as is” meets essential specs. Use of ladder Fast-OR and very low Fast Multiplicity would require partial redesign. Final decision in Q2/02. Exceptional new lot of 48 wafers just delivered –ALICE≈ 24 –NA60 16 –LHCb,..≈ 8 New ALICE lot: optimisation of bump-bonding and wafer thinning –allows some flexibility in deadline for decision on final production

23. 16/11/01GS/ALICE SPD/LHCC Referees 23 Half-Stave Readout Electronics Chain A. Kluge

24. 16/11/01GS/ALICE SPD/LHCC Referees 24 PILOT ASIC CMOS6 0.25  m Rad-hard design Dimensions 4mm x 6mm JTAG controls clock recovery and distribution half-stave data out level conversion multiplexing interface to Gigabit Optical Link (GOL) (serialiser/driver ASIC) currently under test (Nov 01) A. Kluge

25. 16/11/01GS/ALICE SPD/LHCC Referees 25 Bias ASIC - Optical link package Bias ASIC : generates reference levels for the pixel chip –design (≈ 3 months) to start in Jan 02 (EP-MIC) –submission in MPW –might be on critical path for MCM Optical link package (1 laser diode, 2 PIN diodes, overall thickness < 1.4mm) –development under way –functional prototype ≈ end March 02 –full production will take ≈ 3 months

26. 16/11/01GS/ALICE SPD/LHCC Referees 26 Silicon Sensors p+ on n with guard rings, each wafer (5”) has 5 ladders + 13 singles Prototypes –300  m thickness15 wafersavailable –200  m thickness 3 wafersavailable (+ 2 in order) CERN Market Survey MS-3087/EP/ALICE sent out to firms on 12 Nov 01 Closing date: 21 Dec 01 Examination of replies: Jan 02 (2nd week) Invitation to tender will be issued by INFN (Catania/Roma 1) –Committee already appointed –deadline: within Q1/02

27. 16/11/01GS/ALICE SPD/LHCC Referees 27 Bump-bonding - Assemblies First delivered ≈ 10 assemblies: Sensors: p + on n, thickness 300µm Chips: Lot 1 (750µm thick) - unprobed wafers! Assemblies produced by: AMS/ItalyVTT/Finland Indium bumpsPb-Sn solder bumps stand-off ~ 10µmstand-off ~15µm Chip Detector P. Riedler

28. 16/11/01GS/ALICE SPD/LHCC Referees 28 Assemblies - Threshold Scan Threshold measurement: VTT 8 Mean threshold: 21.2 mV RMS: 2.8 mV Similar to measurement on bare chip. P. Riedler

29. 16/11/01GS/ALICE SPD/LHCC Referees 29 Assemblies - Noise Scan Noise measurement: VTT 8 Mean noise: 1.97 mV RMS: 0.24 mV Similar to noise on bare chip. P. Riedler

30. 16/11/01GS/ALICE SPD/LHCC Referees 30 Threshold Scan on Assemblies P. Riedler 50mV ≈ 3,200 e -

31. 16/11/01GS/ALICE SPD/LHCC Referees 31 Assemblies - Source Tests Source tests were carried out on all assemblies, using: ~1600~6100~63 300Electrons RMS ~6keV gammas~22+25 keV gammas (electrons shielded)2.28 MeV electrons Fe 55Cd 109Sr 90Source Bump-bonding quality Calibration Threshold adjustment

32. 16/11/01GS/ALICE SPD/LHCC Referees 32 Assemblies - Sr90 Source Bump-bonding quality Assembly VTT 10 Bias: 80V Sr-source P. Riedler

33. 16/11/01GS/ALICE SPD/LHCC Referees 33 Assemblies - Fe55 Source glue drop No threshold adjustWith threshold adjust P. Riedler

34. 16/11/01GS/ALICE SPD/LHCC Referees 34 Beam Test with Assemblies 13-25 July (Period 1) and 1-9 September, 2001 (Period 2) H4 beam-line in the NA57 area 150 GeV/c pions 10 5 -10 6 particles/spill ~10 x 5 mm 2 beam-focus Scintillator trigger selects 2 x 2 mm 2 beam-spot Period 1: one plane, 2 assemblies tested Period 2: telescope (3 planes), 5 assemblies tested analysis under way

35. 16/11/01GS/ALICE SPD/LHCC Referees 35 Beam Test Set-Up (I) scintillator S3 ~10m two small scintillators orthogonal to each other { C2 C1B Assembly 1 beam MB card power supply x-y table MB card power supply MB card power supply Assembly 0 Assembly 2 C1A Full telescope (for Period 1 only the centre assembly was mounted)

36. 16/11/01GS/ALICE SPD/LHCC Referees 36 Beam Test Set-Up (II)

37. 16/11/01GS/ALICE SPD/LHCC Referees 37 Beam Profile Beam profile in z (425 µm pixels): ~ 7 pixels = 3 mm Beam profile in x ( 50 µm pixels): ~50 pixels = 2.5 mm VTT 12

38. 16/11/01GS/ALICE SPD/LHCC Referees 38 Bias Scan Normalization to scintillating counters - preliminary! Sensor thickness 300  m

39. 16/11/01GS/ALICE SPD/LHCC Referees 39 Cluster Size Analysis (preliminary, from run with 1 assembly)

40. 16/11/01GS/ALICE SPD/LHCC Referees 40 First ALICE Pixel Ladder from VTT

41. 16/11/01GS/ALICE SPD/LHCC Referees 41 Pixel Wafer Probing (I) Each wafer contains 86 ALICE1LHCb chips. Tests carried out on each chip: Current consumption (analogue/digital) JTAG functionality Scan of all DACs Determination of minimum threshold Complete threshold scan of pixel matrix

42. 16/11/01GS/ALICE SPD/LHCC Referees 42 Pixel Wafer Probing (II) Class I Class II Fully functional, but less than 6000 pixels responding to the threshold scan Class III Masking problems, high or asymmetric noise or threshold Class IV Excessive or no current No response from the chip P. Riedler

43. 16/11/01GS/ALICE SPD/LHCC Referees 43 Pixel wafer thinning Pixel wafers will be thinned after bump deposition (processed side protected) VTT has equipment and expertise in this field Preliminary trials with 4” and 8” blank wafers with SPD bump pattern –wafers thinned down to <100  m –backside free from bump imprint Imminent trial with real probed pixel wafers –check if thinning affects performance –determine practical limit Bump-bonding thinned chips and ladders is next major challenge –development program under way –completion expected in June 02

44. 16/11/01GS/ALICE SPD/LHCC Referees 44 Mechanics & Cooling Items to be produced: Carbon fiber support structure: 10 sectors (turbo_like disposition) Two halves cylinder-cone support structure working also as thermal screen towards SDD and air flow channelling Tooling for stave assembly, detector assembly etc. TEST already done: Prototypes of CFSS made out of different CF tape thickness and resin (epoxy, cyanate ester). The final geometry is not yet assessed (sector length, cooling system choice, etc.). The main efforts are on integration scenario definition and cooling system design & test. A. Pepato

45. 16/11/01GS/ALICE SPD/LHCC Referees 45 SPD Sector (II) A. Pepato

46. 16/11/01GS/ALICE SPD/LHCC Referees 46 Cooling Test Bench AB A. Pepato

47. 16/11/01GS/ALICE SPD/LHCC Referees 47 Summary - Planning Pixel ASIC meets essential specs. KGD yield from engineering wafers ≈ 35% Pre-production wafer lot procured Sensors market survey sent out Bump-bonding optimisation and wafer thinning trials in progress FE electronics chain under test Pixel bus prototyping nearly completed Key electronic issues under study: signal integrity on bus, end-stave connections, grounding, power distribution (rad-hard voltage regulators in patch-panels), etc Mechanics & cooling well defined, corrosion study under way ==> choice of coolant Completion of all developments by Q3/02, production to start in Q4/02 Detailed planning reviewed Nov 01 Challenge ahead: detector assembly and integration (ladders, bus, glueing, wire bonding, mounting on sectors, final tests)