1. Semiconductor Device and Processing Technology
Course Tutor
Dr R E Hurley
Northern Ireland Semiconductor Research Centre
School of Electrical & Electronic Engineering
The Queen’s University of Belfast

2. Semiconductor Device and Processing Technology
8. SOI
What is it?
History
What’s it used for?
Description
How to make it
Wafer bonding
Silicon
Insulator
Substrate

3. SOI Technology
The substrate is a thin silicon layer on a thin insulator layer on a silicon substrate.
Reduces parasitic capacitance (higher speed 15%, lower power -20% than equivalent bulk CMOS)
Reduces probability for ‘latch-up’ from radiation (isolation of n and p wells)
Insulator is oxide for CMOS and sapphire for radiation-sensitive devices (e.g. cosmic rays)
First commercial SOI by IBM 1998
Silicon on insulator technology (SOI) refers to the use of a layered silicon-insulator-silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance and thereby improving performance.[1] SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or (less commonly) sapphire. The choice of insulator depends largely on intended application, with sapphire being used for radiation-sensitive applications and silicon dioxide preferred for improved performance and diminished short channel effects in microelectronics devices [2]. The insulating layer and topmost silicon layer also vary widely with application. The first implementation of SOI was announced by IBM in August 1998.[3]

4. Methods of manufacture
SIMOX. (Heavy dose implanted oxygen makes an oxide layer)
Wafer bonding to an oxidised substrate. (splitting away a thin top layer of silicon with wafer splitting)
Wafer Bonding
Top wafer is ‘wasted’ by grinding, etching and polishing
‘Smart-cut’. Hydrogen implanted and expanded by heating.
Porous silicon grown and split by water jets
Stress at interface of Si and SiGe layer.
SIMOX - Separation by IMplantation of OXygen - uses an oxygen ion beam implantation process followed by high temperature annealing to create a buried SiO2 layer.[5][6][7]
SIMOX process
Wafer Bonding[8] [9] - the insulating layer is formed by directly bonding oxidized silicon with a second substrate. The majority of the second substrate is subsequently removed, the remnants forming the topmost Si layer.
One prominent example of a wafer bonding process is the Smart Cut method developed by the French firm Soitec which uses ion implantation followed by controlled exfoliation to determine the thickness of the uppermost silicon layer.
NanoCleave is a technology developed by Silicon Genesis Corporation that separates the silicon via stress at the interface of silicon and silicon-germanium alloy.[10]
ELTRAN is a technology developed by Canon which is based on porous silicon and water cut.[11]
Seed methods[12] - wherein the topmost Si layer is grown directly on the insulator. Seed methods require some sort of template for homoepitaxy, which may be achieved by chemical treatment of the insulator, an appropriately oriented crystalline insulator, or vias through the insulator from the underlying substrate.

5. SIMOX Si is simply implanted with a large quantity of oxygen!
(You can buy this from China)

6. BESOI (bond and etched back SOI)
Wasted
Wafer is bonded to an oxidised wafer and the top ground mechanically away and etched and polished.

7. Smart Cut Technology has 5 key steps
Hydrogen implantation into the active wafer
Hydrophilic wafer bonding
Low T thermal anneal for splitting
High T anneal for bond strength
Final touch polish

8. SMART-CUT Damage What is SOI ?
Silicon on insulator (SOI) is a semiconductor wafer technology that produces higher performing, lower power (dynamic) devices than traditional bulk silicon techniques. SOI works by placing a thin, insulating layer, such as silicon oxide between a thin layer of silicon and the silicon substrate. This process helps reduce junction capacitance, resulting in higher speed and lower power consumption. SOI chips can be as much as 15 percent faster and use 20 percent less power than today's bulk complementary metal-oxide semiconductor (CMOS)-based chips.
In the area of Radio Frequency (RF) and mixed signal applications, SOI offers the opportunity to enjoy the benefit of low noise and high-quality passives. Incorporation of silicide layers such as WSi2 allows the SOI to be modified forming Ground Plane Silicon On Insulator (GPSOI) further enhancing cross-talk reduction.
Placing a silicide layer between the buried oxide and the top silicon device layer converts SOI into Silicon on Silicide On Insulator (SSOI). This technique is aimed mostly at the bipolar transistor with the inclusion of the silicide layer minimising collector series resistance.
Other advantages over bulk silicon include:
Higher Packing Densities
Complete Dielectric Isolation
Radiation Hardness  
Image Image Caption Figure 1. SEM Image of Ion Split SOI Silicon on insulator can be made using many techniques.
Wafer Bonding followed by Precision Grinding and Polishing.
SIMOX: Separation by implantation of oxygen.
Ion Split SOI : Implanation of hydrogen forming a weakened region within the silicon.
BESOI: Bond and Etchback SOI, employing a SiGe etchstop layer.

9. Smart-cut process 3 1 2 4

10. Examples of cracks appearing along line of H or He implant
Annealing at 5000C → expanding hydrogen → cracks
Examples of cracks appearing along line of H or He implant

11. Higher temperature anneals with He produce rows of bubbles
Annealing ~ 8000C

12. Results – GOOD and BAD GOOD Particle voids → defects E = 160keV
Dose = 6 x 1016 cm-2
Oxygen plasma pre-clean
GOOD
Particle voids → defects
The oxygen plasma activation is undertaken in an RIE system which creates particle contamination. This is difficult to remove without reducing bond energy.

13. Scanning electron microscope (SEM) of SOI
Mm-wave reflect-arrays offer flat profile and light weight, combined with many of the useful electrical characteristics of parabolic reflector antennas.  By integrating diodes into the reflect-array structure the array can be made to perform the function of a spatial phase shifter, thereby permitting its use for beam steering applications.
In order to ensure high aperture efficiency, simulation has shown that the series loss resistance of these diodes must be less than 2W.  To effectively minimise diode resistance it is necessary both to tightly control the thickness of the active silicon layer beneath the device junction, and also to provide a low resistance buried layer interconnect to this region.  In addition, mm-wave transmission line losses must also be minimised. 
Such a structure may be implemented using MBE, however this method has the disadvantage of high processing cost.  As a realistic low-cost alternative, this work focussed on the fabrication of SSOI (Silicon on Silicide On Insulator) substrates produced on high resistivity silicon, using ion splitting and two stages of silicon wafer direct bonding.
This technology permitted the production of SSOI substrates with active silicon regions only 0.5µm thick utilising low resistivity tungsten silicide (WSix) as the buried layer interconnect material, thus providing a very suitable substrate for the fabrication of high frequency Schottky barrier diodes.
Si on SiO2 on silicon

14. Smart Cut SOI Final success!
Hydrogen implant 100keV and 6x1016 cm-2
Oxygen plasma and short MSC1 clean
Ramp up to 400°C
Successful Smart-Cut SOI – i.e. NO VOIDS!

15. Importance of wafer bonding for SOI
To produce quality SOI requires:
First Class Bonding Technology!

16. Wafer bonding – process flow Cleaning is the key to good bonding!
Commercial systems now use vacuum for bonding
12 hrs ?
QUB uses ultra-sonic bath (0.01–0.02:1:5 NH4OH:H2O2:H2O, 550C,
20 min)
In clean air at atmosphere
Megasonic cleaning in modified SC1 solution,
(0.01–0.02:1:5 NH4OH:H2O2:H2O, 55 1C,
20 min), rinsing and drying immediately before
bonding to an oxidised wafer (0.5 mm oxide
thickness) in air at room temperature.
Cleaning is the key to good bonding!

17. Requirements for a good bond
Flatness – only 1 – 3 µm required (wafer will bend!)
Micro-roughness < 0.5 nanometres needed.
Cleanliness – no dust, hair, fibres! No organics. (hydrocarbons). No metal ions.
Class 10 cleanroom or better.

18. Good bond needs cleanliness!
Small particle produce large voids
Particle 1µm dia.
Void 1 cm !! wide
Organics outgass during annealing
Metal ions affect electrical properties of devices

19. Model of the bonding process
Hydrophobic – wafer repels water
Hydrophilic – wafer attracts water.
Hydrophilic bonding – wafer has surface layer of oxide
Wafer surface are terminated by OH groups after RCA clean
(NH4OH:H2O2:H2O)
Stage 1
Water fills out gaps up to 6Å and forms Van de Waals and H bonds

20. Model of the bonding process
Stage 2 C
Some water reacts with silicon to form SiO2 + 2h2. Water goes into oxide, finding Si, water may also diffuse out if a path.
Interface water is removed, silanol (Si-OH) groups approach

21. Model of the bonding process
Stage 3 C
AT 8000C all water is driven out and covalent Si-O-Si bonds formed. Full strength only achieved at 11000C
This is a problem where temperature must be limited (4500C, if circuit elements present)
Silanol to covalent bonding (siloxane) is reversible below 425C

22. Low temperature bonding
Bonding silicon to glass at < 5000C
Parameters: Temperature, bias voltage, time.

23. Low temperature bonding
Plasma bonding: The bond strength annealing at < 500C is excellent, but particles are a big problem from plasma reactor.
Oxygen plasma: 30secs only at 200W power. 45 secs only in RCA1. Dry, anneal at < 500C
+ good housekeeping!

24. Problems of plasma bonding
Plasma bonding: early attempts.
Some poor results from another University in 2002
Water vapour believed to be trapped in rough surface produced by plasma bombardment.

25. Key to good SOI is good bond strength
Measure bond strength by inserting a blade between wafers and measure crack propagation length using IR light.
Infra-red (IR) light
Imaging
Blade
Surface energy, γ = 3Etw3tb2/(32L4) mJ/ m2
E is Youngs Modulus

26. Measuring bond strength
View on screen from above wafer
Surface energy, γ = 3Etw3tb2/(32L4) mJ/ m2
E is Youngs Modulus

27. Bonding for micromechanics integrated with microelectronics
CMOS integrated with accelerometer, Sanz-Velasco, 2002
Filter stack, proportional valve, PZT actuator, pressure transducer, heat exchanger, temperature sensor, nozzle
Micromachined thruster module for space applications. 5 bonded wafers, 7 components

28. Schematic cross-section of Schottky diode on SSOI
QUB Diode [silicon on silicide on insulator (SSOI)]
Schematic cross-section of Schottky diode on SSOI

29. Fabrication of silicon on silicide on insulator, (SSOI)Rp
Active Si wafer
LPCVD WSi
LPCVD oxide
Poly-Si
Oxide polish
Ion implantation
SiO2 deposition and rim etch
Discuss here problems of implantation through layers.
Handle Si wafer

30. silicide silicon oxide Handle wafer
Fabrication of silicon on silicide on insulator, (SSOI)
silicide
silicon
oxide
Handle wafer
SSOI has all the advantages of SOI
SSOI gives low resistance buried collector technology
Silicide in SSOI can act as a high diffusivity channel for dopants

31. SEM image of SSOI
Si on WSi2 on SiO2

32. Ultra-thin SSOI substrate (<100 nm)
Present work is combining Smart Cut technology with SSOI to produce ultra thin silicon on silicide
silicon
silicide
oxide
Handle wafer

33. Thin-film SOI: Tsi < 0.5µm Partially-depleted transistors (PD)
Examples of SOI – thin film and ultra thin film
Thin-film SOI: Tsi < 0.5µm Partially-depleted transistors (PD)
Ultra-thin film SOI: Tsi < 50nm Fully-depleted transistors (FD)

34. Low energy effects in ultra-thin smart-cut applications
Elastic collisions give rise to a broad statistical lateral spread.
Uncontrolled channeling can occur up to 20 deg. Off vertical, but may also be used for directing ions precisely to required depth.