1. 2.1 2 ASIC Design Methodology 1. Definition 2. Design Representation(Top-down, B-S-P) 3. Design Objectives 4. ASIC Types 5. ASIC Design Process 6. Cost Analysis Contents

2. 2.2 1. Definition of ASIC qASIC is application-specific. (vs. General-Purpose, Commodity or Standard IC i.e., memory, microprocessor) qASIC can become ASSP(Application-Specific Standard Product) if volume becomes large.(ex:MODEM, disk controller) qASIC integrates many blocks in one chip. (Today’s board is tomorrow’s ASIC.)

3. 2.3 2. Design Representation using Gajski’s Y-chart

4. 2.4 3. Design Objectives low high longhigh performance Per-chip cost(chip area) NRE Cost PTAT(Product Turn-around Time) FPGA Gate array Full-custom BICC

5. 2.5 4. ASIC Types qPLD PAL(device name), PLA(circuit style) ; all AND-OR plane logic(two-level logic) qFPGA qGate Array(with or without embedded block, ex;memory) qStandard Cell(w. or w/o macro) qCompiled block ; datapath, RAM, ROM, multiplier qFull - Custom Semi-custom IC (ASIC in narrow sense)

6. 2.6 Important elements in ASIC Design ASIC design ASIC design System specification in-house CAD tools in-house CAD tools Commercial CAD tools Commercial CAD tools ASIC foundry IP library

7. 2.7 Programmable logic device(PLD) die. The macrocells typically consist of programmable array logic followed by a flip-flop or latch. The macrocells are connected using a large programmable interconnect block.

8. 2.8 Field-programmable gate array(FPGA) die. All FPGAs contain a regular structure programmable interconnect.

9. 2.9 Two-step manufacturing Full-custom fabrication Semi-custom fabrication Standard phasecustom phase

10. 2.10 Standard & Custom Masks Two-step manufacture : First(deep) processing steps Base wafers Customization : contacts & metal layers ASIC Custom masks Custom masks Standard masks Standard masks

11. 2.11 qMaster array = core + I/O pads qCore : - macro-architecture number & distribution of basic core cells embedded(specialized) structures - micro-architecture isolation method : gate or oxide isolation predefined channels or channelless layout available devices : transistors, capacitors, resistors, … NMOS/PMOS transistor count ratio number of contacts to each transistor gate, source or drain spacing between transistors, or transistor pitch identical or variable size transistors relative size of the NMOS and PMOS transistors layout of the basic core cell qI/O pads - number, functional capabilities, size,... Architecture Specifications (gate array)

12. 2.12 qPLDs, PALs, EPLDs : < 2K gates field programmable AND/OR arrays with latches use (E)EPROM or (anti)fuse devices qfield programmable gate arrays(FPGA) : < 5K gates(1972),  100K gates(1998) electrically programmable SRAM, antifuse or EPROM devices logic mapped into predefined blocks programmable interconnections qgate arrays, sea-of-gates(SOG) :  200K gates personalized with metals & contacts standard cell compiled cells datapath, ROM, RAM qmacro-based & full-custom : all mask layers personalized dense & high performance Comparison of Various ASIC Methodologies Rapidly changing designs low volume low complexity High volume complex stable designs

13. 2.13 l Fill the gap between PALs and classical(mask programmable) gate arrays l architecture :  array of configurable logic blocks(gates, multiplexers, flip-flops)  predefined routing channels filled with interconnection wires  wires are programmable programming technology : EPROM, anti-fuse, or SRAM.  SRAM : volatile but reconfigurable configuration Xilinx  EPROM : non-volatile and reprogrammable, Altera  anti-fuse circuits : permanent programming Actel size : up to 10K gate, (now 200K gates) speed is comparable to PALS. Field Programmable Gate Arrays K

14. 2.14 qFirst gate arrays : l one programmable metal layer l fixed contact locations l extensive use of polysilicon for routing l 2- or 3- transistor cell -> 2- or 3-input NAND (NOR) gates qlater improvements : l use several basic cells to implement more complex macros l programmable contacts l second programmable metal layer + vias First Generations of Gate Arrays Predefined channel P N P N

15. 2.15 qCHANNELLESS LAYOUT l suppression of predefeined channels l array entirely filled up with transistors l connections are routed over unused transistors qGATE ISOLATION vs. OXIDE ISOLATION l suppression of the gaps in the diffusion l continuous strips of diffusion with equally spaced transistors l basic cell = 1N & 1P l electrical isolation made by connecting a gate to VSS(NMOS) or VDD(PMOS) qOTHER VARIANTS & IMPROVEMENTS : l embedded arrays l RAM-compatible basic cell l additional metal layers Second Generation : Sea-of-Gates Gate isolation Oxide isolation VDD P N VSS VDD P N VSS

16. 2.16 qADVANTAGES OF GATE ISOLATION : l flexibility in macro width(one transistor increment) l density : transistor gate length smaller than diffusion-diffusion distance l full merging of source & drain qPROBLEMS WITH GATE ISOLATION : l N-and P-gate need to be physically separated l on very large & noisy circuits, glitches on power supply lines may weaken the isolation for short times Gate Isolation vs Oxide Isolation

17. 2.17 Channelled versus Channelless Array Routing problem is simpler OK with only one metal Flexibility in channel definition(position & width) over-the-cell routing higher packing density RAM-compatible supports variable-height cells & macrocells now universally used

18. 2.18 l Simpler l reusability of classical P&R tools l tunable channel width(in fixed increments) l lower density(in terms of gates) l gates are smaller l smaller transistor size Routing Channels l fixed channel width l increased master cell area l large transistor size l both methods can be used together l needs a special macro design Alternate channels : Covering channels :

19. 2.19 qSignal routing : l internal macro connections : metal 1 l external horizontal wires(channels) : metal 1 l external vertical wires : metal 2 l metal 3&4, if any, follow direction of metal 1&2, respectively Metal Usage

20. 2.20 qpower distribution : l primary distribution : horizontal metal 1 lines l secondary distribution : vertical metal 2 lines Metal Usage

21. 2.21 Embedded Structures A part of the core is dedicated to a special function most often : static RAM but also ROM, A/D or D/A converters, PLL, … also : embedded test structures advantages : optimized function, performance, high density drawback s : less versatile array, need to maintain a larger master family(price !) Core is generic and supports various customizations reduced master family -> lower price higher flexibility, e.g. RAM size and location need adapted CAD tools

22. 2.22 BiCMOS Master Architecture(1) Higher gate count(CMOS is denser) TTL or ECL I/Os examples : Hitachi 84 NTT 89(reduced voltage on-chip) now abandoned BiCMOS periphery blocks used for clock buffers, level conversion, … CMOS core : 60% - 95% area example : LSI Direct Drive Array(88)

23. 2.23 BiCMOS Master Architecture(2) Variant of the previous mixed digital/analog applications bipolar part can contain passive elements can be seen as an embedded array example : LSI Logic Higher flexibility in the use of both devices full digital or mixed applications the most used architecture examples : Motorola, AMCC, Hitachi, TI, Toshiba NEC, Fujitsu

24. 2.24 Standard Cell Layout(W=25  m in =0.25  m

25. 2.25 CBIC routing in 2-metal layers

26. 2.26 Datapath composed of datapath cells Datapath cell = Bit Slice  Functional Element

27. 2.27 5. ASIC design process

28. 2.28 6. Cost Analysis Spreadsheet for fixed cost of FPGA MGA and CBIC

29. 2.29 Spreadsheet for Variable cost of FPGA MGA and CBIC

30. 2.30 Product Profit Model

31. 2.31 아무리 바빠도 아무도 간섭할 수 없는 1 시간을 만들고, 그 1 시간에 나만의 깊은 ‘ 그 무엇 ’ 을 생각하라. 결국 그것이 모든 것을 이끌고 간다. 아무리 바빠도 아무도 간섭할 수 없는 1 시간을 만들고, 그 1 시간에 나만의 깊은 ‘ 그 무엇 ’ 을 생각하라. 결국 그것이 모든 것을 이끌고 간다. 인생의 키

32. 2.32 사람들은 새는 주머니를 차고 새로운 정보를 얻으려 뛰어다닌다. 깊이 생각지 않고 하루종일 뛰고 배워도 피곤하고 남는게 없고 항상 남의 꽁무니만 쫓을 뿐이다. 사람들은 새는 주머니를 차고 새로운 정보를 얻으려 뛰어다닌다. 깊이 생각지 않고 하루종일 뛰고 배워도 피곤하고 남는게 없고 항상 남의 꽁무니만 쫓을 뿐이다. 정보매니악에 대한 경고 정보매니악에 대한 경고