1. October 11, 20001

2. 2 Design Consideration USB2 PHY Core Patrick Yu inSilicon Corporation patrick_yu@ieee.org

3. October 11, 20003 Set the Record w This presentation is not about how to design a USB2 PHY Core with UTMI for connectivity to backend logic w This presentation is to share some of what we have learned, in the design of a Hard Core – Reusable IP core – Good for ASIC/SOC and ASSP integration

4. October 11, 20004 Content w System-level Consideration w Core-level Consideration w Testability Consideration w “Ease of Integration” Consideration w Summary

5. October 11, 20005 System-Level Consideration w How would the PHY be used? – Host Controller, Hub Controller, Function Controller – Application specific or SOC

6. October 11, 20006 System-Level Consideration w Characteristics of the applications – Host Controller, when integrated into a PC core logic, needs to support 5 to 8 ports u When integrated into a CE devices like STB and residential gateway, needs 1 to 3 ports – Function Controller is usually application specific u The system environment could be space limited, e.g. still camera u The applications typically require only one port u Usually very concerned with the cost of passive components needed, as well as system cost Continued

7. October 11, 20007 System-Level Consideration w Influence of these characteristics on PHY’s features – 3 speeds: LS @ 1.5Mbps, FS @ 12Mbps, HS @ 480Mbps – Support low-cost crystal for Function Controller, clock generator for Host Controller u Cost difference is typically of 2X – On-chip termination u Saving of 2 pins per port for Host Controller application u Driver input-impedance variation of + 10% for HS become non- issue u Cleaner signal for the receiver – Integration of “pull-up resistors” could improve timing

8. October 11, 20008 System-Level Consideration w What about power? – Can USB 2.0 peripherals ever be bus-powered ? u Probably “not” for discrete USB 2.0 Hub ! – Current budget for LDO & switch-mode regulators, passive components, electro-mechanicals, electronics,

9. October 11, 20009 Current Consumption: Chips System-Level Consideration USB Semiconductor Devices USB1.1 Audio ASSP Philips UDA1331H 50mA @ 3.3V max 48MHz crystal oscillator: startup current @ 15mA typical operating current @ 2.1mA USB1.1 I/F Device ASSP Philips PDIUSBD12 15mA @ 3.6~5.5V operational; 15mA when suspended with oscillator off 6MHz crystal oscillator (clock multiplying PLL to 48MHz) USB2.0 PHY ASSP Philips ISP1501 FS transmit & receive @ 6mA HS receive @ 54mA max. HS transmit @ 100mA max. Suspend mode @ 40mA max. 12MHz crystal input (internal to 30MHz & 480MHz) Power Switch - MIC2075 Micrel Semiconductor Max. supply current @ 160mA O/P leakage current @ 10mA for Host & Hub applications LDO Regulator – MIC5207 Micrel Semiconductor Quiescent current = 0.01 ~ 5mA Ground pin current @ I L = 100mA: 80mA ~ 170mA; Ground pin current @ I L = 100mA: 720mA ~ 2mA; Ground pin current @ I L = 150mA: 1.8mA ~ 3mA for Peripheral applications

10. October 11, 200010 System-Level Consideration Current Consumption: Devices USB Peripheral Devices SanDisk CompactFlash (8 ~ 300Mbytes) 32~45mA @ 3.3V read 46~75mA @ 5V 32~60mA @ 3.3V write 46~90mA @ 5V SanDisk MM Card (4 ~ 32Mbytes) < 33mA @ 3.3V read < 23mA @ 2.7V < 35mA @ 3.3V read < 27mA @ 2.7V LexarMedia Cflash (160 ~ 256Mbytes) 65mA @ 5V read/write 45mA @ 3.3V read/write IBM Compact Flash Reader 255mA @ 5V www.apricorn.com Iomega Zip 250 ~ 450mA @ 5V (moving to 3.3V) Design uses switch-mode regulator USB-to-10/100 Ethernet Bridge 285mA @ 5V 450mA @ 3.3V www.linksys.comwww.cadmusmicro.com USB-to-10Mbps Ethernet Bridge 120mA @ 5V www.silicom.co.il USB-to-56K modem 40mA Full-ON Mode < 0.5mA Sleep Mode www.sharkmm.com

11. October 11, 200011 Summary System-Level Consideration w Pin-count and termination are important for Host Controller, but …… w High-power bus-powered USB 2.0 peripherals are feasible, but watch for current budget – Consumption by transmitter, receiver, oscillator circuitry, PLL, DLL, DPLL, 5V short-circuit protection u Un-initialized mode budget of 100mA u Initialized mode budget of 500mA u Suspend mode of 500mA or 2.5mA – Consumption of LDO or Switch-mode regulator – Voltage drop across passive components

12. October 11, 200012 Core-Level Consideration Architecture

13. October 11, 200013 Core-Level Consideration w Flexible system partitioning – Support LS/FS/HS, yet allowing the use of legacy SIE w Design should be immune to noise – Differential technique for clock circuitry – Noise isolation techniques in layout w Portability to different processes w Test Bus for analog circuitry w Support for single-port and multi-port – Common block, plus duplicated block – Allow tiling or stackable layout DLLT’xcvrR’xcvr Logic PLL C.O. DLLT’xcvrR’xcvr Architecture

14. October 11, 200014 UTMI USB 1.1 UHCI / OHCI SIESIE SIESIE SIESIE UTMI* PHY (digital) UTMI PHY (mixed-signal) UTMI* PHY (digital) UTMI PHY (mixed-signal) UTMI* PHY (digital) UTMI PHY (mixed-signal) UTMIUTMI UTMIUTMI UTMIUTMI USB 2.0 EHCI Core-Level Consideration w UTMI is a direct fit for HS/FS peripheral application w UTMI* for host application – Additional signals are needed to support multi ports and hybrid OHCI / UHCI & EHCI implementation u For example, direct access to FS/LS transceivers by legacy SIE of USB1.1 Host Controller

15. October 11, 200015 UTMI Core-Level Consideration w UTMI* for OHCI / UHCI and EHCI for direct connection to the individual UTMI* PHYs UTMIUTMI UTMIUTMI UTMI*UTMI* USB 1.1 UHCI / OHCI UTMIUTMI UTMIUTMI UTMIUTMI USB 2.0 EHCI UTMI* PHY (digital) UTMI PHY (mixed-signal) UTMI* PHY (digital) UTMI PHY (mixed-signal) UTMI* PHY (digital) UTMI PHY (mixed-signal)

16. October 11, 200016 Transceivers Core-Level Consideration w Fully static – The receiver will remain off until the packet transmission is done u Careful with the control timings, because small overlap of the receiver and transmitter on-timing will be necessary u Turning off the DLL certainly help, but what about turn-on time ? – Receivers must accommodate a wide range of common mode voltage while within the sensitivity/threshold spec for LS/FS/HS

17. October 11, 200017 Transceivers Continued Core-Level Consideration w Transmitter should provide the highest quality signal – Matching the rise time and fall time are tricky u Multi-phase turn-on enable symmetrical output – Eliminate as much jitter as possible from the output w Power consumption is critical for bus-powered applications – 3.3V voltage source are necessary to interface 5V tolerant I/Os – 5v short-circuit protection unfriendly to low-voltage process

18. October 11, 200018 Core-Level Consideration w Common PLL block to supply 480MHz clock to the rest – Any jitter in the PLL will propagate to the other blocks u PLL is a low-pass filter, hence any jitter of the reference clock matter – All differential design will increase power consumption – Clock distribution: balanced and synchronous – Start-up time could be critical Clocks w Phase Interpolator provides phase increment (single-ended) of PLL synthesized clock (pecl differential) – Interpolates between taps of the VCO to facilitate digital clock recovery at DLL – Non-linearity of transfer function does not matter as long as maximum tap size is small enough PECL to CMOS Converters PECL PH0 PECL PH1 PECL PH2 PECL PH3 PECL PH4 CMOS PH0 CMOS PH1 CMOS PH2 CMOS PH3 CMOS PH4 CMOS PH5 CMOS PH6 CMOS PH7 CMOS PH8 CMOS PH9 CMOS PH10 CMOS PH11 CMOS PH12 CMOS PH13 CMOS PH14 CMOS PH15 CMOS PH16 CMOS PH17 CMOS PH18 CMOS PH19

19. October 11, 200019 Clocks Core-Level Consideration w DLL for high-speed digital design – Recover the 480MHz clock from the incoming HS data – Lock to the sync pattern must be within 12 HS bit times w DPLL for full/low-speed: low-speed digital – Over-sample the incoming FS/LS data @ 48MHz

20. October 11, 200020 Clocks Continued Core-Level Consideration w Oscillator circuitry for crystal – Amplifier design approach provides better control of crystal drive and more predictable performance over supply voltage noise – Small start-up current and nominal operating current consumption – Usable output a.s.a.p

21. October 11, 200021 Core-level Consideration w Design should be immune to noise – Differential technique w Isolation technique applied during layout of the Hard Core – Clean external voltage source – On-chip de-coupling capacitors to reduce impact of supply noise – Substrate separation ? – Sea-Wall to isolate the high-speed analog blocks – Triple-well process, but expensive Noise Containment V DD Nwell-ringNwell-ring Psub-ringPsub-ring Analog Circuits Psub-ringPsub-ring V SS * V SS

22. October 11, 200022 Analog IP Core Testability Consideration w Debugging and Verification – Test Bus for analog circuitry u Tap into key points of analog circuitry to measure voltage, current, resistance, etc. u Multiplexed with other primary I/Os of the chip should be ok, but, never cut corner as they can be business threatening – Push vs Pull u BIST cost gates and not vendor-neutral u “Loop-back + Stopping Clock + Scan-chain” w UTMI Test Modes

23. October 11, 200023 Analog IP Core Testability Consideration w Support for manufacturing – Full scan (difficult for high-speed digital circuitry like DLL & elasticity buffer) – Loop-back logics to automate transmitter and receiver testing – PLL bypass – Functional test vectors optimized for tester time – Corner-case analysis w Verification with Test Chip & USB PlugFest

24. October 11, 200024 Analog IP Core “Ease of Integration” Consideration w USB2 PHY Core is a high-speed Analog PHY IP Core – Would licensees want a “hard” or “soft” core? u Hard Core is process/library dependent u Soft Core is process/library INdependent – Can design database – GDSII – be simply drop in? u Layout and placement u Test signals routing

25. October 11, 200025 Analog IP Core Continued “Ease of Integration” Consideration w USB2 PHY Core is a high-speed Analog PHY IP Core – Would licensees need to do circuit tweak for different fab. @ same process? u Impact on the scope of deliverables – Is the analog circuitry susceptible to digital switching noises ? u On-chip decoupling capacitors, triple-well process, sea-wall layout, …… – How to identify problem on a “finished” design: SOC ? u Test Buses, full-scan, loop-back…….

26. October 11, 200026 Summary w UTMI-compliant PHY IP Core is a sophisticated design – Hard Core is fool-proof for integration purpose – Soft Core is difficult to use and requires substantial in-house analog expertise w Correct design consideration mean a good re-usable IP Hard Core – Careful planning of feature objective before committing your internal resource and development schedule – Consult your provider (internal or external) in detail before committing your resource and money – Consult your provider (internal or external) in detail before committing your resource and money u No zero TCO please ! w It is important for the consumers and the providers of the PHY IP Core to have the right expectation