1. 1 The Physical Structure (NMOS) Field Oxide SiO2 Gate oxide Field Oxide n+ Al SiO2 Polysilicon Gate channel L P Substrate D S L W (D) (S) Metal n+ (G) Poly contact

2. 2 Transistor Resistance : Two Components: Drain/ Sources Resistance: R D(S) = Rsh x no. of squares+ contact resistance. Channel Resistance : Depends on the region of operation: L W (D) (S) n+ (G) R S Rch R D Linear Saturation

3. 3 Transistor Geometry

4. 4 Transistor Geometry- Detailed

5. 5 NMOS Operation-Linear Process Transconductance uA/V 2 for 0.35u, K’ (Kp)=196uA/ V 2 Gate oxide capacitance per unit area  ox = 3.9 x  o = 3.45 x 10 -11 F/m t ox Oxide thickness for 0.35 , tox=100A o Quick calculation of Cox: Cox= 0.345/tox (A o ) pf/um 2  = mobility of electrons 550 cm 2 /V-sec for 0.35  process K N =K’. W/L

6. 6 NMOS Operation-Linear Effect of W/L Effect of temperature Rds W/L W temp  Rds W

7. 7 Variations in Width and Length W eff W drawn WDWD W D 1. Width Oxide encroachment W eff = W drawn -2W D 2. Length Lateral diffusion L D = 0.7Xj L eff = L drawn -2L D L drawn L D L eff L D polysilicon

8. 8 Large Transistors u R channel decrease with increase of W/L of the transistor

9. 9 Semiconductor Resistors Resistance R= p( l /A) = (p/t). ( l /w ) = Rsh. ( l /w ) Rsh = Sheet resistance  / For 0.5u process: N+ diffusion : 70  / M1: 0.06 P+ diffusion : 140  / M2: 0.06 Polysilicon : 12  / M3: 0.03 Polycide:2-3  /P-well: 2.5K N-well: 1K w current l t (A)

10. 10 Semiconductor Resistors Al n+ Diffusion n+ Field oxide polysilicon Polysilicon Resistor Diffusion Resistor SiO2

11. 11 Semiconductor Capacitors 1. Poly Capacitor: a. Poly to substrate b. Poly1 to Poly2 2. Diffusion Capacitor n+ (N D ) depletion region substrate (N A ) bottomwall capacitance sidewall capacitances

12. 12 Dynamic Behavior of MOS Transistor Prentice Hall/Rabaey

13. 13 SPICE Parameters for Parasitics Prentice Hall/Rabaey

14. 14 SPICE Transistors Parameters Prentice Hall/Rabaey

15. 15 Modelling: Resistance 1. Resistance: Rint= Rsh [l/w] Rsh values for 0.35u CMOS Process: Polysilicon 10  / Polycide 2  / Metal1 0.07  / Metal II 0.07  / Metal III 0.05  / Contact resistance: PolyI to MetalI 50  Via resistance: Metal I to Metal II 1.5  Via resistance: Metal II to metal III 1. 

16. 16 CMOS Inverter: Steady State Response V DD V V out V V in = V DD V in = 0 R on R V OH = V DD V OL = 0

17. 17 Switching Characteristics of Inverters Transient Response

18. 18 Computing the Capacitances V DD V V in V out M1 M2 M3 M4 C db2 C 1 C gd12 C w C g4 C g3 V out2 Fanout Interconnect V out V in C L Simplified Model

19. 19 Computing the Capacitances

20. 20 Delay Definitions

21. 21 Step Response Fall Delay Time: TPHL Vin I DN V in = 5 V in = 4 V in = 3 VDD=5V Vin G S D D G S Vo GND MP MN CL VDD Vo VDD-VT MN OFF Saturation Linear (VDSAT)

22. 22 Step Response- Fall time, tf vin vo 1-n td1 td2 1 0.1 0.9 t f =~ k is a constant t r =~ k is a constant 0.1

23. 23 Step Response-tPHL Vin Vo VDD-VTN Vx td1 td2 vin vo 1-n td1 td2 VDD 1 0.5 VDD/ 2 Assume normalized voltages vin= Vin/ VDD vo= Vo/ VDD n = V TN / VDD p = V TP / VDD t PHL =td1+td2

24. 24 Step Response Rise Delay t PLH and Rise Time t r VDD Vin G S D D G S Vo GND MP MN CL VDD (P= - 0.2)  0.1

25. 25 Factors Influence Delay Inverter Delay,td = (t PHL +t PLH )/2 The following factors influence the delay of the inverter: Load Capacitance Supply Voltage Transistor Sizes Junction Temperature Input Transition Time

26. 26 Delay as a function of V DD

27. 27 Delay as a function of Transistor Size u t PHL and t f decrease with the increase of W/L of the NMOS u t PLH and t r decrease with the increase of W/L of the PMOS

28. 28 Temperature Effect u Temperature ranges: commercial : 0 to70 0 C industrial: -40 to 85 0 C military: -55 to 125 0 C u Calculation of the junction temperature t j = t a +  ja X Pd u Effect of temperature on mobility u Delay and speed implications

29. 29 Effect of Input Transition Times rr Vin Vo The delay of the inverter increases with the increase of the input transition times  r and  f t PHL = (t PHL ) step + (  r /6).(1-2p) t PLH = (t PLH ) step + (  f /6).(1+2n)

30. 30 Define  = (W/L)p/(W/L)n u For Equal Fall and Rise Delay K N =K P  =  n /  p u For Minimum Delay dt D /d  = 0  opt = Sqrt (  n /  p ) Transistor Sizing

31. 31 Power Dissipation in CMOS Two Components contribute to the power dissipation: »Static Power Dissipation –Leakage current –Sub-threshold current »Dynamic Power Dissipation –Short circuit power dissipation –Charging and discharging power dissipation

32. 32 Static Power Dissipation G S D D G S Vo VDD GND B B MP MN Leakage Current: P-N junction reverse biased current: i o = i s (e qV/kT -1) Typical value 0.1nA to 0.5nA @room temp. Total Power dissipation: P sl =  i 0.V DD Sub-threshold Current Relatively high in low threshold devices Vin

33. 33 Analysis of CMOS circuit power dissipation n The power dissipation in a CMOS logic gate can be n expressed as n P = P static + P dynamic n = (VDD · I leakage ) + (p · f · E dynamic ) n Where p is the switching probability or activity factor n at the output node (i.e. the average number of output n switching events per clock cycle). n The dynamic energy consumed per output switching event is defined as E dynamic =

34. 34 Analysis of CMOS circuit power dissipation The first term —— the energy dissipation due to the Charging/discharging of the effective load capacitance C L. The second term —— the energy dissipation due to the input-to- output coupling capacitance. A rising input results in a V DD  - V DD transition of the voltage across C M and so doubles the charge of C M. C L = C load + C dbp +C dbn C M = C gdn + C gdp

35. 35 n distributed, n voltage-dependent, and n nonlinear. n So their exact modeling is quite complex. The MOSFET parasitic capacitances Even E SC can be modeled, it is also difficult to calculate the E dynamic. On the other hand, if the short-circuit current i SC can be Modeled, the power-supply current i DD may be modeled with the same method. So there is a possibility to directly model i DD instead of i SC.

36. 36 Schematic of the Inverter

37. 37

38. 38 The short-circuit energy dissipation E SC is due to the rail- to-rail current when both the PMOS and NMOS devices are simultaneously on. E SC = E SC_C + E SC_n Where and Analysis of short-circuit current

39. 39 Charging and discharging currents n Discharging Inverter Charging Inverter

40. 40 Factors that affect the short-circuit current For a long-channel device, assuming that the inverter is symmetrical (  n =  p =  and V Tn = -V Tp = V T ) and with zero load capacitance, and input signal has equal rise and fall times (  r =  f =  ), the average short-circuit current [Veendrick, 1994] is From the above equation, some fundamental factors that affect short-circuit current are: , V DD, V T,  and T.

41. 41 Parameters affecting short cct current For a short-channel device,  and VT are no longer constants, but affected by a large number of parameters (i.e. circuit conditions, hspice parameters and process parameters). C L also affects short-circuit current. I mean is a function of the following parameters (t ox is process- dependent): C L, , T (or  /T), V DD, W n,p, L n,p (or W n,p / L n,p ), t ox, … The above argument is validated by the means of simulation in the case of discharging inverter,

42. 42 The effect of C L on Short CCt Current

43. 43 Effect of t r on short cct Current

44. 44 Effect of Wp on Short cct Current

45. 45 Effect of timestep setting on simulation results

46. 46 Thank you !