1. Circuit Level Models Of CMOS Technology Transistors Prof. John Choma, Jr. University of Southern California Department of Electrical Engineering-Electrophysics University Park: MC: 0271 Los Angeles, California 90089-0271 213-740-4692 (USC  ) 626-915-0944 (FAX  ) 818-384-1552 (CELL  ) johnc@almaak.usc.edu Fall 2001 Semester EE 348: Lecture #04 Canonic Cells Of Analog MOS/CMOS Technology Prof. John Choma, Jr. University of Southern California Department of Electrical Engineering-Electrophysics University Park: MC: 0271 Los Angeles, California 90089-0271 213-740-4692 (USC  ) 626-915-0944 (FAX  ) 818-384-1552 (CELL  ) johnc@almaak.usc.edu Jchoma1106@aol.com Spring 2003 Semester

2. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 115 Lecture Overview Common Source Amplifier  Model  Low Frequency Performance  High Frequency Performance Broadband RF Amplifier  Transfer Function  I/O Impedances  Design Scenario Source Follower  Model  High Frequency Compensation Common Gate  Model  High Frequency Performance  Cascode Configurations

3. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 116 CMOS Common Source Amplifier Assumptions  Transistors Are Saturated:  Transistor Drain And Source Series Resistances Are Negligible Objectives  Voltage Gain Transfer Function  Frequencies Of Poles And Zeros

4. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 117 CMOS Small Signal Model Capacitances For Deep Submicron Technology  Input Capacitance (Tens Of fF):  Feedback Capacitance (Few fF):  Output Capacitance (Tens -To- Hundreds Of fF): Resistance Parameter (A Few -To- Tens Of K  ):

5. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 118 CMOS Amplifier Voltage Gain Pole Relationships Zero Zero Frequency Gain Magnitude

6. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 119 CMOS Amplifier Time Constants Time Constant Due To Poles (“a”)  Sum Of Open Circuit Time Constants With Source Nulled  Time Constant Of Any One Capacitor Is Computed With All Other Capacitances Open Circuited And With Source Signal Nulled Time Constant Due To Zeros (“c”)  Sum Of Open Circuit Time Constants With Response Nulled  Time Constant Of Any One Capacitor Is Computed With All Other Capacitances Open Circuited And With Response Nulled Foregoing Is General Time Moment Theory For Any nth Order Circuit

7. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 120 Time Constant Due To Poles a  a i + a o + a f

8. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 121 Time Constant Due To Zeros c  c i + c o + c f

9. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 122 Bandwidth Estimation Approximate Bandwidth (B)  Assume |cB| << 1 (Frequency Of Zero Is Much Larger Than B)  Assume bB 2 << 1 (Frequency Of High Frequency Pole Is Large) Comments  Crude First Order Bandwidth Estimate  Requires Real Poles Only  Requires Nominally Dominant Pole Frequency Response  Practical Design Guideline  May Not Be Supremely Accurate Bandwidth Estimate But Small “a” Is A Necessary (But Not Sufficient) Condition For Broadband Response  An Examination Of The Constituent Terms Of “a” Identifies Energy Storage Elements/Time Constants That Dominantly Limit Theoretically Achievable 3-dB Bandwidth

10. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 123 Frequency Response Metrics Critical Frequency Relationships Unity Gain Frequency -  u Pole Dominance Metric  k p = p 2 /  u  k p > 1 Implies Amplifier Is A Dominant Pole Circuit

11. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 124 Negligible Feedback Capacitance Poles Zero At Infinity Unity Gain Frequency For p 2 >> p 1 Pole Dominance Metric Comments  Negligible Feedback Presumption Valid When No Feedback Capacitance Is Appended  Pole Dominance Requires g m1 R s < C o /C i  Dominant Pole Response Requires k p > 1  Typical For First Stage; Atypical For Interstages  Unity Gain Frequency Is Effectively The Ratio Of Driver Transconductance -To- Output Capacitance Ratio

12. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 125 Significant Feedback Capacitance Poles/ Zero Unity Gain Frequency Pole Dominance Metric Comments  Significant Feedback Presumption Valid When Feedback Capacitance Is Appended, As In Pole Splitting Compensation  Pole Dominance Requires Large Source Resistance  k p > 1  Typical For Interstage; Atypical For Front End First Stage  Unity Gain Frequency Is Determined By Time Constant Formed Of Source Resistance And Feedback Capacitance

13. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 126 Frequency Response: Unstable Potentially Unstable Because Second Pole Lies At Frequency That Is Smaller Than Unity Gain Frequency; That Is, k p < 1

14. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 127 Frequency Response: Stable Likely To Be Stable Because Second Pole Lies At Frequency That Is Larger Than Unity Gain Frequency; That Is, k p > 1

15. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 128 Match-Terminated Common Source Assumptions  Very Large Transistor Channel Resistance  Low Frequency Considerations Only For Initial Study  Biasing Network Has Been Simplified To Expedite Analyses Match Termination  Circuit Can Be Designed For R in = R out When R s = R l  Match Termination Implies R s = R in = R out = R l  R  Match Termination Useful For Cascaded Stages

16. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 129 Match-Terminated Concept Terminations  Single Stage: R s = R in = R out = R l  R  Cascade: For All Three Stages, R s = R in = R out = R l  R Comments  Loading Effects On Each Stage Effectively Eliminated  Reminiscent Of Transmission Line Loaded In Its Characteristic Impedance  Results In Maximum Power Transfer At All I/O Ports Gain: A v = V os /V s Gain: V os /V s = A v 3

17. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 130 Match-Terminated Analysis Critical Parameter Is G f = 1/R f Performance Indices Return Ratios  R T : Thévenin Resistance Seen By R f With V s = 0  R TO : Thévenin Resistance Seen By R f With V os = 0

18. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 131 I/O Impedances Straightforward Substitution Of Results Into I/O Equations Comments  If R i = R o And R s = R l, R in  R out  More Commonly, R i >> R s And R o >> R l  Then R i = R in = R out = R l  R Requires R f = g me R 2  Note That Match Terminated Assumption Mandates R << R s, R l

19. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 132 Match-Terminated Gain Straightforward Substitution Of Results Into Gain Equation Design  Calculate g me For Desired Gain And Required Match Resistance  Calculate R ss Based On Requisite g me  Calculate Required R f Based On Required R And Computed g me

20. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 133 Inductive Output Impedance Match Terminated Output Impedance  Inductive Because Of Gate-Source Capacitance, C gs  Potentially Troublesome With Capacitive Loads Computation  R Is Zero Frequency Output Impedance  a: Time Constant Of C gs With Current I x Constrained To Zero  b: Time Constant Of C gs With Voltage V x Constrained To Zero Inductive If b > a

21. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 134 Inductance Computation Computations Effective Inductance

22. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 135 Comments On Inductive Output Presumptions  Very Large Channel Resistance (Reasonable For 50  Load)  Very Large Input Port Resistance, R i (Reasonable For 50  Load)  Very Large Output Port Resistance, R o (Reasonable For 50  Load)  Negligible Gate-Drain Capacitance (Reasonable For Self-Aligning Gate Technology And Possibly For Common Gate Cascode)  Drain-Bulk Capacitance Absorbed Into Load Termination Output Port Inductance  Effective Inductance Estimate Is Low By About 20% -To- 30% Due To Foregoing Presumptions  Magnitude Is Generally Below A Nanohenrie Or So  Can Cause Ringing/Settling Time Problems For Inappropriate Capacitive Loads  Incurs Non-Match-Terminated Conditions At Very High Signal Frequencies

23. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 136 Source Follower Model Modifications Simplified Model

24. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 137 Source Follower Model Source Follower Common Source Observation  Topologically Identical Models  Gain And Pole Frequency Expressions Derive From Respective Common Source Results With Mere Changes In Circuit Branch Variable Notations

25. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 138 Source Follower Gain Transfer Function Poles And Zeros Approximation Note Left Half Plane Zero

26. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 139 Dominant Output Port Capacitance Approximate Pole And Zero Frequencies Pole Dominance (p 2 >> p 1 )  Requires  Implications  Small Source Resistance  Large Device Unity Gain Frequency

27. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 140 Response Compensation Transfer Function Feedforward Capacitive Compensation  Incorporate Capacitance C c Across Gate-Source Terminals  Choose C c Such That C c + C gs >> C o  May Be Difficult For Large Source-Bulk Or Load Capacitances  Requires Negligible Threshold Modulation Factor Gain And Bandwidth (B) Results

28. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 141 Compensated Follower Transfer Function Net Output Port Capacitance Effect Of Feedforward Capacitance Is Effectively To Bypass Transistor At High Signal Frequencies

29. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 142 Follower Output Impedance Dominant Pole/Zero Approximation Compare Pole/Zero Time Constants  Inductive Impedance Requires b > a  Capacitive Impedance Requires a > b  Calculate “a” As Sum Of Open Circuit Time Constants With I x = 0  Calculate “b” As Sum Of Open Circuit Time Constants With V x = 0

30. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 143 Time Constants — Z out Due To Zero Due To Pole Effective Inductance Inductive Condition  Satisfaction Likely For Large Source Resistance  Satisfaction Likely For Gate-Source Compensation Capacitance

31. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 144 Source Follower Input Admittance Input Admittance Voltage Ratio Effective Input Capacitance

32. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 145 Common Gate Amplifier

33. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 146 Common Gate Model/Performance

34. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 147 Common Gate Gain Parameters Open Loop Gain  Magnitude: |A io (j ω )| < 1  Dominant Pole Most Likely Is Established By C o Loop Gain  Magnitude < 1  Magnitude Is Actually Much Smaller Than One And Smaller Yet At High Frequencies Closed Loop Gain

35. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 148 Common Gate I/O Impedances Input Impedance Output Impedance I/O Impedances Are Both Capacitive And Approximately Dominant Pole Frequency Functions

36. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 149 Common Gate Summary Current Gain Frequency Response  Less Than Unity Current Gain Magnitude At All Frequencies  Dominant Pole Is Established By Net Output Port Capacitance  Input Resistance Is Small  Output Resistance Is Very Large I/O Impedances  Low Frequency Input Impedance Is Small  Low Frequency Output Impedance Is Very Large  Both I/O Impedances Are Strongly Capacitive  Input Impedance Is Capacitive Only To The Extent That The Transistor Gate Is Biased By A Low Impedance Supply Principle Applications  Current Buffer With Capacitive I/O Ports  Common Source-Common Gate (CS-CG) Cascode  Useful In Transconductor Circuits  Not As Effective As Bipolar Cascode Because Of Very Small Gate- Drain Capacitance Of Common Source Driver

37. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 150 CS—CG Cascode Architecture Performance Results Derive From General Common Gate Disclosures; Note Substitutions Below Dominant Pole Likely Established At High Impedance Output Port

38. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 151 Cascode Circuit Performance Voltage Gain  About The Same As For Common Source Alone  Gate-Drain Capacitance Of M1 Is Small, Thereby Mitigating Miller Effect On C gd1 Output Resistance  Very Large  M2 Channel Resistance Multiplied By Approximately g m2 /g o1 Pole  If R l Is Resistance Of Current Source, p Is Very Small  Result Is Integrator Having Approximate Unity Gain Frequency Equal To Gain-Bandwidth Product

39. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 152 Wilson Current Amplifier Assumptions  All Transistors Biased In Saturation Regime  Aspect Ratio Evaluate Performance  Current Gain  Input Resistance  Output Resistance

40. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 153 Model Manipulation Circuit Equations Diode M2 Modeled By Two Terminal Net Conductance

41. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 154 Wilson Small Signal Model Feedback

42. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 155 Wilson Small Signal Performance Current Gain  Determined By Relative Device Geometries  Best Suited For Current Signal Processing I/O Resistances  Small Input Resistance  Very Large Output Resistance  Excellent Current Sink

43. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 156 CS—Wilson Cascode Dominant Pole Established At High Resistance Output Port Functions As A Cascode With Current Gain  Allows Load Resistance To Be Reduced By Factor Of Wilson Current Gain To Get Voltage Gain Equal To Conventional Cascode  Lower Load Resistance Spells Lower Output Port Time Constant And Hence, Increased Bandwidth, To The Extent That Output Port Capacitance Establishes Dominant Pole Small Signal Equations Low Frequency Voltage Gain

44. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 157 Bandpass Low Noise Common Source Inductors  Assuming Infinite Q (Only In Academe), They Contribute No Noise  Real Inductors Have Finite Q And Finite Self Resonant Frequency Input Topology  Allows Input Impedance Match To Source Resistance  Maximum Power Transfer Critical Because Of Low RF Signal Power  Match Is Only Bandpass → OK For Low Noise RF Applications Biasing Not Shown

45. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 158 Bandpass Model Modifications Ignore Gate-Drain Capacitance  Self-Aligning Gate Technology  Possible Use Of Common Gate Cascode  Small Device Thickness (W)  Note k g = 1 Inductors  Account For Winding Resistance (Finite Q)  Ignore Self Resonance In L gg (Analytical Tractability)  Include Self Resonance In L ss  Capacitance Across Terminals Of Inductor Winding  Absorb Capacitance Into C sb ; Replace C sb By C ss > C sb Miscellany  Ignore Channel Resistance, r o (Reasonable For Typical Loads)  Ignore C db By Ultimately Absorbing It Into Load Termination Objective  Demonstrate Bandpass Nature Of Amplifier  Demonstrate Match Terminated Input (Signal) Port

46. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 159 Source Terminal Impedance Source Lead Impedance Parameters  Undamped Resonance  Quality Factor Comments  Desire Infinitely Large Undamped Resonant Frequency  For ω s → ∞

47. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 160 Modified RF Bandpass Model Source Lead Current  Max Z ss  Approximation  Small Inductance  High Quality Factor (Low R ss )  Connect Bulk To Source (λ b = 0) Input Port Impedance

48. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 161 RF Input Port Input Impedance Assume Large ω s  Small Inductance  Connect Bulk To Source Terminal

49. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 162 Input Port Matching Resonate L in And C in With Carrier Frequency, ω c, Of Signal Match Input Resistance With Source Resistance  Matching Accomplished Via L ss  Low Noise, Since No Resistance Is Explicitly Used For Matching  Since L ss Is Used For Resistance Match, L gg Affords Additional Design Degree Of Freedom For Setting Center Frequency Resultant I/O Relationships

50. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 163 Basic RF Amplifier Approximate Model  Large r o  Small C gd  Small g mb Z dd Is Same Form As Z ss  Q Of Inductor (Resistance R dd )  Drain-Bulk And Output Port Capacitances (C dd = C db + C o ) Biasing Is Incomplete Z in = R s @ ω = ω c

51. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 164 RF Amplifier Gain Gain Relationships Voltage Gain Design Options  Double Tuning  Single Tuning  Butterworth, Tchebyschev, Bessel Or Other Optimization

52. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 165 Comments On RF Design Options I/O Gain Single f Tuning  ω d = ω c  Difficult To Implement  Parametric Uncertainties  Gate-Drain Feedback Capacitance Renders Port Tuning Non-Independent  Gain At Signal Carrier Frequency Double Tuning  Optimize Pole Locations For Butterworth Or Other Response Form  ω c ≠ ω d ; Q c ≠ Q d  Difficult To Implement Reliably On Chip For Foregoing Reasons Single (Input Port) Tuning  Ensure ω d Large In Comparison With Highest Frequency Of Interest  Requires Very Small Geometry Device Because Of C dB

53. University of Southern California/Choma EE 348, Spring 2003: Lecture #04 166 Circuit Implementation Of RF Cell Transistor M1  Basic Transconductor  Bulk Transconductance Is Mitigated Transistor M2  Common Gate Cascode  Mitigates Miller Multiplication Of C gd In M1  Must Have Large W For Low Transconductance Transistor M3  Sets Biasing For M1  Behaves As Current Mirror Since, Assuming Ideal Inductors, Gate-Source Biasing Of M1 And M3 Are Identical  Note No Bias Current Through Resistor R b Stage Engineering  Operates At Low Biasing Voltages  Can Be Realized Differentially