1. University of Connecticut Virtual Lab Carl DiFederico, Shane Tobey, Kasim Ward Graduate Student Advisor: Qihang Shi Senior Faculty Advisor: Mohammed Tehranipoor Electrical & Computer Engineering

2. All Rights Reserved 2 Table of Contents Project Overview Abstraction of Module 1 (Hardware) Abstraction of Module 2 (Software) Hardware Model and Requirements Software Model and Requirements Upcoming Deadlines

3. All Rights Reserved 3 Project Overview The overarching project is a portion of the virtual lab, under CHASE This goal of this project is to create a board with a web- interface that will detect out of current to determine if DUT is counterfeit The CDEB project will actually contain two interlinked projects 1) Continuation of the first CDEB by last year’s senior design team 2) A web interface and server dedicated to collecting chip information from customers

4. All Rights Reserved 4 Abstraction of Module 1 The specific types of counterfeit chips to be detected are recycled and out of spec copies Our team assumes that recycled chips should have noticeable wear characteristics In this case we are attempting to detect out of spec transient and leakage current

5. All Rights Reserved 5 Abstraction of Module 1 The current board in use is the first- generation board, designed by last year’s senior design team The current design calls for the chip in question to first be programmed An FPGA sends a test signal to the board DC power and AC clock supplies are controlled by a computer An oscilloscope collects the results

6. All Rights Reserved 6 Abstraction of Module 1 The board currently is designed for the 8051 For our project we will continue to test the 8051 Our goal is to order more boards, 10 in total and run python code to switch between boards

7. All Rights Reserved 7 Abstraction of Module 2 Module 2 is the proposed web interface The web interface will include a loggable website which will allow data, a server that holds log information, data upload, and will hold the output data gathered from the oscilloscope and compiled by the computer

8. All Rights Reserved 8 Abstraction of Module 2 The web interface must gather the following information: General customer stats, name address, email, etc. Pin count and information Chip name, model # Voltage specifications Test code, with pin directions

9. All Rights Reserved 9 Abstraction of Module 2 The server must: Hold the customer information Send the engineer relevant information Run the Python code when the engineer launches the program Connect to the hardware modules and hold the resulting excel files

10. All Rights Reserved 10 Hardware Model and Requirements The current hardware model includes replicating the current first generation board into a total of 10-20 boards We have found some problems with the first generation board, namely fragility. The wires need to be more secure. We will create an array of boards with a modular mounting bracket/base. The boards will be connected to the server by a modular bus. The bus will communicate with a microcontroller that dictates which board is enabled for input. We also need to switch the output to the oscilloscope, i.e. connect the oscilloscope probe to the bus

11. All Rights Reserved 11 Hardware Model and Requirements Fig. Proposed Hardware Model

12. All Rights Reserved 12 Hardware Model and Requirements Hardware Requirements/ Items to be bought: Boards Brackets Bus Interface Microcontroller to switch between boards Use of spare computer to be reformatted as a dedicated server, or a new computer

13. All Rights Reserved 13 Software Model and Requirements The software portion of the project will entail changes in the code to support 10-20 boards Python code must be modified to allow for dynamic changes in voltage specifications for leakage test (for within a tolerance) The server will use Microsoft Server OS (free for students) The server must store the identifier of each chip and the engineer must put each identified chip in the correct slot A Microcontroller must be programmed to select along the bus

14. All Rights Reserved 14 Upcoming Deadlines and Goals Make the First Generation Board wiring more secure Parts research Sep 23 (M) Project Statements Due Sep 30 (M) Project Specifications Due