1. 1 Lecture 1 EE587 SoC Design & Test Partha Pande School of EECS Washington State University pande@eecs.wsu.edu

2. 2 Lecture 1 Lecture 1 Design and Technology Trends Overview

3. 3 Lecture 1 Recent Trends 1.5GHz Itanium chip (Intel), 410M tx, 374mm 2, 130W@1.3V 1.1 GHz POWER4 (IBM), 170M tx, 115W@1.5V –if these trends continue, power will become unmanageable 150Mhz Sony Graphics Processor, 7.5M tx (logic) + 280M tx (memory) = 288M tx, 400mm 2 10W@1.8V –if trend continues, most designs in the future will have a high percentage of memory Single-chip Bluetooth transceiver (Alcatel), 400mm 2, 150mW@2.5V –required 30 designers over 2.5 years (75 person-years) –if trend continues, it will be difficult to integrate larger systems on a single chip in a reasonable time

4. 4 Lecture 1 Multi-Core Design Intel’s 80-core chip –In 65-nm technology with 80 single-precision, floating point cores delivers performance in excess of a teraflops while consuming less than 100 w. –A 2D on-die mesh interconnection network operating at 5 GHz provides the high-performance communication fabric to connect the cores. Interconnects are the biggest bottleneck –We need to look beyond the metal/dielectric-based planar architectures –Optical, 3D integration and Wireless are the emerging alternatives

5. 5 Lecture 1 Multi-core applications Nokia Sparrow Intel LARRABEE

6. 6 Lecture 1 Three-Dimensional Integrated Circuits Coming in a big way Multiple Layers of Active Devices Driven by –Limited floorplanning choices –Desire to integrate disparate technologies (GaAs, SOI, SiGe, BiCMOS) –Desire to integrate disparate signals (analog, digital, RF) –Interconnect bottleneck 6 2D IC3D IC As small as 20µm

7. 7 Lecture 1 Photonic Communication High bandwidth photonic links for high payload transfers Limitations on switch architecture More than 4-port designs are complex On-chip integration of photonic components

8. 8 Lecture 1 On-Chip RF/Wireless Interconnects Replace long distance wires Use of waveguides out of package or IC structures like parallel metal wires Chang et al. demonstrated Transmission Line based RF interconnect for on chip communication –Not really wireless

9. 9 Lecture 1 Lower Latency and Energy Dissipation Three Dimensional Integration Optical Interconnects Wireless/RF Interconnects Novel interconnect paradigms for Multicore designs

10. 10 Lecture 1 MOS Transistor Scaling (1974 to present) Scaling factor s=0.7 per node (0.5x per 2 nodes) Metal pitch Technology Node set by 1/2 pitch (interconnect) Gate length (transistor) Poly width

11. 11 Lecture 1 Ideal Technology Scaling (constant field)

12. 12 Lecture 1 Technology Nodes 1999-2019 180nm 130nm 90nm 65nm 45nm 32nm 22nm 16nm 1999 2001 2004 2007 2010 2013 2016 2019 0.7x 0.5x N-1 N N+1 Two year cycle between nodes until 2001, then 3 year cycle begins.

13. 13 Lecture 1 MPU Clock Frequency Trend Intel: Borkar/Parkhurst

14. 14 Lecture 1 10 100 1000 Dec-83Dec-86Dec-89Dec-92Dec-95Dec-98 80386 80486 Pentium Pentium II Expon. MPU Clock Frequency Trend Intel: Borkar/Parkhurst Dec-99Dec-00Dec-01 Dec-02 10000 Forward projection may be too optimistic P4

15. 15 Lecture 1 MPU Clock Cycle Trend (FO4 Delays) Intel: Borkar/Parkhurst

16. 16 Lecture 1 where  is ratio of Parasitic output Capacitance to gate capacitance C IN C load 1X 4X16X Optimal Sizing - FO4 Concept Use FO4 delay as optimal delay

17. 17 Lecture 1 Clock cycle trend

18. 18 Lecture 1 MPU Trends - Moore’s Law 4004 8008 8080 8085 8086 286 386 486 Pentium ® proc P6 0.001 0.01 0.1 1 10 100 1,000 10,000 ’70’80’90’00’10 Transistors (MT) 2X Growth in 2 Years! Transistors Double Every Two Years Source: Intel

19. 19 Lecture 1 More MPU Trends Pentium ® Pro proc Pentium ® proc 486 386 286 8086 8085 8080 8008 4004 41 36 32 28 1 10100’70’80’90’00’10 Die size (mm) ~7% growth per year ~2X growth in 10 years ~40mm Die in 2010? Source: Intel

20. 20 Lecture 1 What about power in the future? 0.1 1 10 100 1,000 10,000 ’71’74’78’85’92’00’04’08 Power (Watts) 4004 8008 8080 8085 8086 286 386 486 Pentium ® processors Power Projections Too High! Hot Plate Nuclear Reactor Rocket Nozzle Sun’s Surface Source: Intel

21. 21 Lecture 1 Problem with Power and Speed Power knob running out –Speed == Power –10W/cm 2 limit for convection cooling, 50W/cm 2 limit for forced-air cooling –Large currents, large power surges on wakeup –Die size will not continue to increase unless more memory is used to occupy the additional area –additional power dissipation coming from subthreshold leakage Speed knob running out –Historically, 2x clock frequency every process generation 1.4x from device scaling 1.4x from pipelining, hence fewer logic stages (from 40-100 down to around 16 FO4 INV delays) –Clocks cannot be generated with period < 6-8 FO4 INV delays –Around 14-16 FO4 INV delays is limit for clock period Unrealistic to continue 2x frequency trend!

22. 22 Lecture 1 Low-Power Application: PDA 0.18um / 400MHz / 470mW (typical) CPU I-cache 32KB D-cache 32KB I2C FICP USB MMC UARTAC97 I2S OST GPIO SSP PWMRTC DMA controller LCD Cnt. MEM Cnt. PWR CPG SDRAM 64MB Flash 32MB LCD Peripheral Area 4 – 48MHz Data Transfer Area 100MHz Processor Area Max 400MHz MM Application MP3 JPEG Simple Moving Picture 6.5MTrs. Available Time 6-10Hr USB MMC KEY Sound

23. 23 Lecture 1 Trends in Low-Power Design Content Today, SoC designs contain embedded processing engines such as CPU and DSP, and memory blocks such as SRAM and embedded DRAM As we scale technology and keep power constant how does the amount of logic vs. memory change? Consider the following assumptions to develop trends for on- chip logic/memory percentages Die size is 100mm 2 Clock frequency starts at 150MHz increases by about 40% per technology node Average power dissipation in limited to 100mW at 100 o C Initial condition at Year 2001: area percentage 75% logic, 25% memory

24. 24 Lecture 1 ASIC Logic/Memory Content Trends Source: Dataquest (2001)

25. 25 Lecture 1 Design Trend: Productivity Gap

26. 26 Lecture 1 Designing a 50M Transistor IC Gates Required~12.5M Gates/Day (Verified)1K (including memory) Total Eng. Days12,500 Total Eng. Years35 Cost/Eng./Year$200K Total People Cost$7M Other costs (masks, tools, etc.)$8M Actual Cost is $10-15M to get actual prototypes after fabrication.

27. 27 Lecture 1 Productivity Gap Deep submicron (DSM) technology allows hundreds of millions of transistors to be integrated on a single chip Number of transistors that a designer can design per day (~1000 gates/day) is not going up significantly New design methodologies are needed to address the integration/productivity issues  “System on a chip” Design with reusable IP (Intellectual Property) –new design methodology, IP development –new HW/SW design and verification issues –new test issues

28. 28 Lecture 1 SoC Design Hierarchy SOC consists of new logic blocks and existing IP New Logic blocks Existing IP including memory Each logic block can be implemented by newly designed portion and a re-use portion based on IPs Newly designed portion Re-use portion including memory

29. 29 Lecture 1 SoC Platform Design Concept SoC Verification Flow System-Level Performance Evaluation Rapid Prototype for End-Customer Evaluation SoC Derivative Design Methodologies System-level performance evaluation environment HW/SW Co-synthesis SoC IC Design Flows Application Space Methodology / Flows: Foundation Block MEM FPGA CPU Processor(s), RTOS(es) and SW architecture *IP can be hardware (digital or analog) or software. IP can be hard, soft or ‘firm’ (HW), source or object (SW) *IP can be hardware (digital or analog) or software. IP can be hard, soft or ‘firm’ (HW), source or object (SW) Scaleable bus, test, power, IO, clock, timing architectures + Reference Design Foundry-Specific Pre-Qualification Programmable IP SW IP Hardware IP Pre-Qualified/Verified Foundation-IP*

30. 30 Lecture 1 Purpose of this Course This course addresses SoC design & test in DSM technologies The goal is to present an overview of the various issues from “Systems to Silicon” to provide a perspective on what is happening in technology and design. It is a very broad subject, one that industry is grappling with on a daily basis – one course cannot address all the issue properly We will begin with the Systems Level and work our way down to the Circuits Level The projects, presentations, and assignments will provide in- depth analysis of the subjects that are of interest to you

31. 31 Lecture 1 Syllabus –Three broad categories –System on chip design and design for testability –Role of interconnects in contemporary SoC Design –Importance of Power and Low power SoC design methodology

32. 32 Lecture 1 References Analysis and Design of Digital Integrated Circuits - In Deep Submicron Technology, Hodges, Jackson and Saleh, McGraw- Hill, Third Edition, 2004 Essentials of Electronic Testing for Digital, Memory and Mixed- Signal VLSI Circuits by M. L. Bushnell and V. D. Agrawal, Boston: Springer, 2005, ISBN 0-7923-7991-8 Journal Papers, Conference Papers, Course Notes.

33. 33 Lecture 1 Assignments There will be several homework and reading assignments. In reading assignments students are expected to read research papers and submit summaries. The reading list will be available on the course website. In class, you will be told which papers you should review. Each student will have the opportunity to present one paper to the class. The list of papers will be available in the course website. Each student should choose one of the listed papers.

34. 34 Lecture 1 Project One Design Project List of possible projects will be provided You are free to choose your own project. In that case Instructor’s approval is needed.