1. 3D Integration for Integrated Circuits and Advanced Focal Planes
Fermilab Colloquium
February 28, 2007
Craig Keast, Brian Aull, Jim Burns, Nisha Checka, Chang-Lee Chen, Chenson Chen,
Mike Fritze, Jakub Kedzierski, Jeff Knecht, Brian Tyrrell, Keith Warner, Bruce Wheeler, Dave Shaver, Vyshi Suntharlingam, Donna Yost
MIT Lincoln Laboratory
Title slide showing Lincoln team members.
*This work was sponsored by the Defense Advanced Research Projects Agency under Air Force contract #FA C Opinions, interpretations, conclusions, and recommendations are those of the authors and are not necessarily endorsed by the United States Government . 1 1

2. Outline A brief history of CMOS scaling
Drivers behind “Moore’s Law” and their future outlook
The potential of “Next Generation” technologies beyond silicon CMOS
3D circuit integration technology and applications
Summary
Outline for the presentation.

3. A Few Metrics
Vacuum tube (early 1900’s) – transistor (1949) – integrated circuit- IC, “chip” (1959)
During the first 10 years of the chip’s development the US government bought the majority of all ICs produced
Today the US Government purchases are a few percent of the market
Today’s microprocessors contain >500 million transistors and occupy ~2-3 cm2 area
Equivalent number of vacuum tubes would cover an area equal to ~250 football fields
First ICs cost ~$120 and contained 10 transistors ($12/transistor), today’s microprocessors cost ~$500 and contain 500,000,000 transistors ($ /transistor)
If this cost scaling was applied to the automobile industry a $100,000 Porsche 911(turbo) would now cost < 1 cent
A few metrics to help put the phenomenal scaling trends (transistor density and cost) of “Moore’s Law” into perspective.

4. Silicon – The Material Enabling the IC (Semiconductor Wafer Preparation)
Silicon makes up
25.7% of the earth’s crust
Sand
300 mm
Single-Crystal Ingot
Wafer Saw
Slide showing how we arrive at high-quality silicon material starting with sand which makes up >25% of the earths crust and ending up with single crystal silicon wafers on which modern integrated circuits are built.
Silicon’s Oxide (SiO2 ) is a KEY attribute of this material’s success

5. 35 Years of CMOS Scaling and Process Improvements
IC cross section
10 mm
Self-Aligned Gates
Self-Aligned Silicides
CMP
Tungsten Plugs
1 mm
Halo Implants
Backend
Copper Interconnect
Low-k Dielectric
Strained Silicon
100 nm
Technology Node
CMOS Replaces Bipolar
For High Performance Computing
High-k Dielectric???
Slide providing a high-level summary of the major technology enhancements introduced into commercial CMOS fabrication as a function of both minimum feature size in the integrated circuit and year of introduction. The enhancements are shown for both frontend (shown in yellow) and backend (shown in orange) process changes.
CMOS Starts to Replace
III-V for Some RF Applications
Frontend
10 nm
Presumed Limit
to Scaling
Bulk Silicon
SOI
????
1 nm
1970
1980
1990
2000
2010
2020
Year

6. Drivers Behind Moore’s Law
Smaller feature sizes
Pack more features in given silicon area
Lower cost per function
Smaller transistors are faster
Smaller transistors and wires consume less energy
Bigger chips
More functions on one chip reduces packaging and integration costs, reduces power, improves reliability
Bigger wafer sizes
More chips per wafer; wafer processing cost for bigger wafers rises more slowly than number of transistors/wafer
Manufacturing know-how
Faster machines, higher yields, better tool utilization
More clever device, circuit, and process design
Pack more in a given area, even for a given feature size
“Equivalent scaling”: next generation performance through improved process/materials: SiGe, SOI, strained silicon
Slide summarizing the major drivers behind Moore’s Law.

7. Shrinking Feature Size….
Human Hair
~75 m
Another slide helping to put the extremely small scale of modern microelectronics in perspective. A leading edge 65-nm process technology can build the equivalent of 40,000 transistors on the cross-section of a human hair. .
0.18 m
180 nm
feature .
~40,000 (65-nm node) transistors could fit on cross-section

8. Lithographic Tools Current State of the art (>$25 M)
~10’
Current State of the art (>$25 M)
65 nm resolution
 = 193 nm
0.93 NA (n sin)
> 1013 pixels/wafer
~ mm wafers/hour
Wafer & mask move 100’s of mm/s during exposure
Let me start with an introduction to lithographic tools in general. The whole point of this $20M machine is to transfer the information encoded on the mask to a photosensitive layer on the wafer here. The reason it costs so much is because of the incredible resolution and speed specifications which it has to meet.
The resolution is controlled by the wavelength of the light, the index of refraction, and the numerical aperture which is essentially a measure of how good the lens is. The lens acts essentially as a low pass filter on the pattern and the NA defines the cutoff spatial frequency. In addition, these tools are fast, cranking out 1014 pixels per hour which means that the wafer and the mask are moving at 100s of mm/s during the exposure.
4x reduction

9. Optical Lithographic Resolution
Rayleigh criterion for resolution W
30x improvement in resolution over 25 years
l from 436 nm to 193 nm
sin q from 0.35 to 0.93
k1 from 0.6 to 0.35
n from 1 to 1
Now approaching limits
l limited by materials and sources
sin q < 1
k1 > 0.25
n ???
The major key to the success of the semiconductor industry has been the fantastic increase in function per unit cost over the past 30 years or more. One of the major factors enabling this has been the ability to pack more and more circuits into the same area and in order to do this, the patterns which define those circuits must, of course, get smaller and smaller. The resolution of the optical lithography used to define those patterns is given, to a good approximation, by the Rayleigh equation here. As you can see, this resolution has improved 30-fold in the past 25 years due to systematic work on the terms on the right hand side. Lambda, the exposure wavelength, has moved from almost blue deep into the ultraviolet through progress in light sources and optical materials. Theta, the half angle of the cone of light used in the exposure, which is essentially a measure of the information processing capability of the lens, has similarly improved by more than a factor of two due to great improvements in lens design and fabrication. K1 which is really a measure of how hard you have to work for a given resolution has also improved by almost a factor of two due a whole toolbox of optical tricks collectively know ans resolution enhancement techniques. The final term on the right hand side of the equation, the index of refraction, has remained unchanged during that whole time. Rightly or wrongly, it was felt throughout this time that the other terms were easier targets for improvement.
However, each of these terms is approaching its limits with only incremental room for improvement. The further reduction of wavelength is severly limited by the lack of transparent optical materials. The fluorides can go down into the 150nm and perhaps as low as 120nm but, as many of you know, the difficulties of 157nm lithography have put much of its development on hold for now. Shorter wavelengths would require new sources and all-reflective optics which pose their own challenges. The beam half angle is, of course, limited to 90 degrees and k1 is limited by basic optical theory to 0.25 so progress on those two fronts will soon reach a hard physical limit. The index of refraction remains, however, and the basic principle of immersion is to improve resolution by increasing that index.
Slide Courtesy M. Switkes, MIT-LL

10. Liquid Immersion Interference 27-nm Half Pitch
High-index fluids have been designed and synthesized (n157 = 1.50)
Enable coupling of light from prism to wafer
No need for solid contact – liquid gap of 2 mm is used
Immersion fluid
Substrate
sin q = 0.87
Spacer
Prism
Si mirror
While solid immersion is conceptually straightforward, for practical reasons it is advantageous to have a coupling fluid. We have developed such an immersion fluid, whose index is high enough that at the 60-degree incidence it couple light to the wafer. Its absorption at 157 nm is moderate, so the gap is limited to ~ 2micron. The resolution is still that determined by the index of the prism – 27 nm.
157 nm light
CaF2
Slide Courtesy M. Rothschild, MIT-LL

11. Optical Lithography at the Nanometer Level
10 nm
100 nm
9 nm
Cross-sectional photograph of a 9 nm gate-length transistor built at MIT-LL in Shown for a size reference in a 10-nm gold particle attached to a strand of DNA. Silicon has been a nano-scale technology for many years.
10 nm gold particle attached to Z-DNA antibody. (John Jackson & Inman. Gene [1989] 84, )
9-nm polysilicon gate on ultra-thin
SOI fabricated at MIT-LL using 248-nm PSM optical lithography (2001)
at MITLL
9 nm polysilicon gate fabricated

12. But will the devices work?
It is likely that we can pattern the smaller feature sizes needed to maintain CMOS scaling….
But will the devices work?
Clearly we can make nano-scale features, but will the devices built using these feature sizes work well?

13. Prognosis For Moore’s Law Benefits
Historically, CMOS scaling has resulted in simultaneous improvements in cost per function, circuit (and system) speed, power consumption, and packing density
Will continued scaling give us the same benefits?
Higher Speed?
Lower Cost?
Historically, CMOS scaling has resulted in simultaneous improvements in cost per function, circuit (and system) speed, power consumption, and packing density. Each new technology generation has brought progress on all three fronts. The next three slides will provide a historical and future perspective on each of these three vectors.
Lower Power? 1 1

14. Lower Cost Prognosis For Moore’s Law Benefits
Past
Scaling (s) increases components per unit area as s2
Wafer size increase gives more chips per wafer
Increasing cost of equipment outweighed by huge increase in number of transistors made per wafer
Mask Set Cost
Future Issues
Skyrocketing equipment costs…Today’s state-of-the-art production facilities cost ~4 billion dollars
NRE (e.g. >$1M mask sets) and productivity issues favor large volume production of “generic” components
Increasing consolidation/pooling of fabrication resources and use of Taiwanese “Super Fabs” TSMC and UMC (China and India next?)
History and potential future of CMOS cost. Cost scaling has been the principle driver fueling Moore’s Law, We have gone to smaller feature sizes and larger wafers because it results in lower cost transistors. However, mask, tool, and fabrication facility costs are growing dramatically. This leads to fabrication facility consolidation, many of which are being build overseas. 1 1

15. Lower Power Prognosis For Moore’s Law Benefits
Past
Supply voltage (V) scales as 1/s
Capacitance (C) scales as 1/s
Energy per op scales as CV2  1/ s3
 Voltage scaling from 5V to 1V accounted for 25X reduction in power, just by itself
Passive and Active Power vs Gate Length
Stove top
Future Issues
Power supply voltage only projected to drop 2X over next 15 years (1.0 to 0.5 V)
Subthreshold device operation?
 Scaling energy per op is critical to long endurance battery powered systems and to supercomputers (getting power in and heat out)
Prognosis for lower power slide. Standby (leakage power) of modern integrated circuits is now approaching the “on” power of the circuits. More energy efficient computation will be necessary as we move into the future.
(~1985)
E. J. Nowak, IBM J. Res. & Dev., Vol. 46, No. 2/3, p. 173 1 1

16. Higher Speed Moore’s Law in Trouble
Processor Speed (INTEL)*
4 GHz
Gate Oxide Dielectric*
Research
Production
Gate
Channel
Prognosis for increase speed. Here Moore’s Law has run into a problem. CPU speed stopped increasing in 2003 with the 90-nm node technology. The principal reason for this is that the transistor gate oxide stopped scaling at this node. We can not make this oxide thinner then it’s current ~1.2 nm thickness without suffering excessive tunnel current leakage through the gate dielectric.
CPU speed has stalled for the first time in 35 years, with no processor able to break through the “4-Ghz barrier”
Why?...Gate oxide scaling has stopped at Tox~1.2nm in 2003, at the 90-nm technology node (~3-4 monolayers)
Only heroic integration efforts, such as use of strained-Si, have made small dents in the CPU speed barrier
Need a workable High-k gate dielectric in order for performance scaling to continue
*D. A. Muller, Nature Materials V 4, pg. 645 (2005)

17. Future High Performance Device “frontend” Possibilities
Continue with Si CMOS. Some possible alternative silicon futures are:
CPU speed could be maxed out – future improvements will come from reduced cost and higher density and integration “multi-core” chips
High-k could save the day – if not tomorrow, maybe in 10 years
A perfect high-k gate dielectric will enable CPU speeds to increase until the next tunneling limit (source-to-drain) at the 10nm-node
Changes in device architecture could take the pressure off the gate oxide, and CPU speed will continue to advance at a slower rate
FDSOI and FinFET lets Tsi scale instead of Tox
No high-k
With high-k
This slides begins a series of slides that discuss the potential future options for increased performance including alternative gate dielectrics (no one yet investigated beats the current silicon dioxide-based gate dielectric).
Thin silicon devices (e.g. FinFETs) over some improvement but not like we have been accustomed to for the last 35 years.
Intel - components research (IEDM2003)

18. Future Possibilities (Cont’d)
A future with transistors, but without silicon:
Germanium-based devices
Improved mobility, at the expense of many other semiconductor properties
Carbon-based devices. Several flavors:
Carbon nanotubes: Have better device properties than Si, but are very difficult to integrate (thus far)
Graphite devices: Difficult to turn off
Molecular devices: Have not been demonstrated to work better than Si
Other transistor possibilities which don’t use silicon, Germanium and Carbon-based devices.

19. Future Possibilities (Cont’d)
A future without transistors:
Josephson-junction-based logic
Demonstrated and works, but at 4K
Real speed and power advantages unclear
Quantum Computation
Can’t execute traditional code, even theoretically
But can solve Schrödinger's equation blazingly fast, and factor very large numbers
Cross Point Arrays – nanowire, molecular
Too simple for general purpose logic, if complexity is increased to meet logic constraints the result is a transistor
MEMS, protein, spin logic – too early to evaluate
Device structures which are not transistors

20. Potential Technology Roadmap
Estimated Performance
Potential Technology Roadmap
Silicon devices
Research Required
Alternate Si
Structures
FDSOI
FinFET
Perfect high-k
Germanium devices
Carbon-nanotube
devices
Graphite devices
Molecular devices
A chart summarizing the major possibilities plotted in estimated performance vs research required space. Other than enhancements to silicon-based devices it looks like carbon based devices hold some potential future promise. However, there is a lot of research and development that will be required before these devices can “replace” silicon.
Spintronics – no evaluation possible, insufficient experimental data
Possible global directions for high performance logic technology in the next 20 years considered in this study, and graphical summary of their evaluations when possible

21. Future Technology Highlights: Carbon Nanotubes (CNTs)D
SWNT
100 nm
VDS = -0.1,-0.2,-0.3 V
L ~ 50 nm
L~30 nm
VDS=-0.3 V 10 -8 -6 -I DS
(A) -1 V G
(V)
1 nm
(Drawing and AFM from CEA website)
Some published results from Stanford University on carbon nanotubes showing impressive device performance. Transistor drive currents that are 10x higher than silicon devices. The problem is sorting and placing the carbon nanotubes.
Example of experimental CNT device from Stanford
Features: metal gate, high-k dielectric, metal source/drain
High performance: 10x Si device of same geometry
Putting tubes were they are needed is a problem
REF: A. Javey, et al. Nano Lett, 2004.

22. Future Technology Highlights Thin Graphite - Graphene
REF: K.S Novoselov et al., Science, V. 306, 22 October 2004, p. 666
Few monolayer graphite device SEM and electrical characteristics at T=70K
Graphite has high mobility of >10,000 cm2/Vs (~15x Si)
Graphite is a semi-metal (semiconductor with band-gap of 0eV)
Difficult to turn off, a fundamental challenge
Proven planar techniques could be used in fabrication
Planar geometry of devices eliminates majority of integration difficulties of carbon nanotubes
MIT-LL has begun to explore this material system
Leveraging layer transfer, materials, and microelectronic fabrication expertise at the Laboratory
Graphene (mono layer of graphite) offers a potential solution the sorting and placement problem of carbon nanotubes. The planar nature of this material system allows the application of standard IC patterning techniques to determine where you build devices. One of the major challenges with graphene is figuring out how to turn this semi-metal material into a semi-conductor by opening up a band gap. MIT-LL has begun to look at this challenge.

23. The Integrated Circuit Interconnect “backend” Challenge
Relative Wiring Delay vs Feature Size*
Typical Process Cross-Section*
Cu Metal
Low-k
Dielectric
Global
Interconnect
(up to 5)
Intermediate
Interconnect
(up to 8)
A graph and figure from the ITRS roadmap showing how the relative delay of the longer wires in chips is becoming a bigger concern with each new generation technology.
Local
Interconnect
Active
Device
*From 2005 International Technology Roadmap for Semiconductors (ITRS)

24. Wire Length Distribution in 90 nm Node IBM Microprocessor*
Very Long Wires
Shorter Wires 2D 3D
Public IBM data showing the interconnect wire length distribution in a 90 nm node IBM microprocessor and stating that most of the power consumption is dominated by the charging and discharging of the long wire in a chip.
>50% of active power (switching) dissipation is in microprocessor interconnects
>90% of interconnect power is consumed by only 10% of the wires
*After K. Guarini IBM Semiconductor Research and Development Center

25. Range of Wire in One Clock Cycle*50
100
150
200
250
300
1995
2000
2005
2010
2015
700 MHz
1.25 GHz
2.1 GHz
6 GHz
10 GHz
13.5 GHz
Year
(20 mm x 20 mm Die)
Process Technology (nm)
From 2003 ITRS Roadmap
Slide based on a public presentation by Prof Amarasinghe on the MIT campus showing the single-clock-cycle reach across a 20 mm x 20 mm chip as a function of clock frequency (Based on the 2003 ITRS Roadmap). Slide will be used to make two points. First the clock of chips has actually stalled at ~4 GHz do to the inability to scale that gate oxide thickness below ~1.1 nm. Second, that 3D integration is way to allow more devices to be reached in a single clock cycle.
3D Integration increases accessible active devices
*After S. Amarasinghe, MIT Laboratory for Computer Science and Artificial Intelligence

26. Motivation for 3-D Circuit Technology
Reduced
Interconnect Delay
High Bandwidth
m-Processors
Exploiting Different
Process Technologies
Advanced
Focal Planes
Mixed Material
System Integration
Slide showing the potential areas where 3D integration might have a strong impact.

27. Pad-Level “3D Integration” Die Stacking
Stacked-Die Wire Bonding
Stacked Chip-Scale Packages
1 mm
Slide showing to commercial companies that offer “pad-level” 3D integration TODAY. Multi-tier wire bonded chip stacks shown on the left and chip-scale package stacking shown on the right. This talk will focus on the development of 3D integration technologies targeted at the device level.
ChipPAC, Inc.
Tessera, Inc.
In Production!

28. Approaches to High-Density 3D Integration (Photos Shown to Scale)
10 mm
Photo Courtesy of RTI
3D-Vias
Tier-1
Tier-2
10 mm
Tier-1
Tier-3
Tier-2
3D-Vias
10 mm
Slide showing “to scale” several different approaches to 3D circuit integration. Including (on the left) traditional bump bonds which are used to interconnect two circuit layers. (middle) A bulk-silicon-based through wafer via approach being pursued by several research organizations. (right) Lincoln’s approach based on SOI layer transfer. Note the much smaller size and 3-layer integration demonstrated by the MIT-LL approach.
Bump Bond used to
flip-chip interconnect
two circuit layers
Two-layer stack with insulated vias through thinned bulk Si
Three-layer circuit using MIT-LL’s SOI-based vias

29. Advantages of Silicon-on-Insulator (SOI) for 3-D Circuit Integration
Handle Silicon
Buried Oxide
Bonding Layer
SOI Cross-Section
Oxide
~675 mm
~6 mm
The electrically active portion of an integrated circuit wafer is < 1% of the total wafer thickness
Buried oxide layer in SOI provides ideal etch stop for wafer thinning operation prior to 3D integration
Full oxide isolation between transistors allows direct 3D via formation without the added complexity of a via isolation layer
SOI’s enhanced low-power operation (compared to bulk CMOS) reduces circuit stack heat load
The MIT-LL 3D-integration process exploits unique attributes of silicon-on-insulator (SOI) technology. The buried oxide layer in SOI provides an ideal etch stop for the wafer thinning operation. The full oxide isolation between transistors allows direct 3D via formation without the added complexity of a via isolation layer. MIT-LL also uses FDSOI CMOS which consumes less power for the same performance when compared to a bulk CMOS technology which will reduce the heat-load in the 3D stack.

30. 3-D Circuit Integration Flow-1
Fabricate circuits on SOI wafers
SOI wafers greatly simplify 3D integration
3-D circuits of two or more active silicon layers can be assembled
Wafer-1 can be either Bulk or SOI
Buried Oxide
Wafer-1
Handle Silicon
Buried Oxide
First slide of a three-slide series showing cross sections of the MIT-LL 3D-integration process. It starts with three fully processed circuit wafers. The first wafer in the stack can be either bulk or SOI, the remaining wafers must be SOI-based.
Wafer-2
Handle Silicon
Buried Oxide
Wafer-3
Handle Silicon

31. 3-D Circuit Integration Flow-2
Invert, align, and bond Wafer-2 to Wafer-1
Wafer-1
Wafer-2
Wafer bond
Handle Silicon
Buried Oxide
Remove handle silicon from Wafer-2, etch 3D vias, deposit and CMP damascene tungsten interconnect metal
Second slide in the series: Wafer-2 is inverted and IR-aligned to wafer-1 and a low-temperature oxide bond is formed between the two wafers. After the bond cycle, the handle-silicon of wafer-2 is removed by a wet chemical process. 3D vias are formed using lithography, plasma etching, CVD tungsten plug fill.
“Back Metal(s)”
Tier-2
IC2
Concentric 3D Via
Tier-1
Wafer-1
Handle Silicon

32. 3-D Circuit Integration Flow-3
Invert, align, and bond Wafer-3 to Wafer-2/1-assembly, remove Wafer-3 handle wafer, form 3D vias
IC2
Wafer-1
Handle Silicon
IC3
Tier-1
Tier-2
Tier-3
Etch Bond Pads
IC2
Wafer-1
Handle Silicon
IC3
Tier-1
Tier-2
Tier-3
Third slide in the series: The process is iterated to add tier-3. The final step opens-up the underside of the bond pads on tier-3.
IEEE Trans. on Electron Devices, Vol. 53, No. 10, October 2006

33. 3D-Specific Enabling Technologies
1.2
1.4
1.6
1.8
2.0
2.2
2.4
1 hr.
10 hr. E a
=0.14eV
500
450
400
350
300
250
200
150
T(oC)
275 o
C, 10 h
1000/T (oK-1)
100
1000
10000
Ea=0.14eV
275oC, 10 hr
Surface Energy (mJ/m2)
Low temperature oxide-bond process
Slide showing the three technologies that need to be developed in order to enable the three integration process at MIT-LL, Precision wafer-to-wafer alignment, low temperature oxide bonding and the high-density 3D-via.
Bond Interface
Precision wafer-wafer alignment
High-density 3D-Via

34. 4-Side-Abuttable Mosaic Focal Planes
Tier-1: 100% fill-factor silicon photodetector layer
Tier-2: CMOS address and readout layer
1024 x 1024 Image
4 x 4 Tiled Array
(mock-up)
Image obtained from the first 3D-integrated wafer pair.
Imager Cross-Section
(8 mm Pixel Pitch)
Image acquired at 10 frames/sec
(Background Subtracted, Pixel Yield > 99.9%, 3.8M transistors)
Presented at 2005 ISSCC

35. 3D-Integrated, 3-Tier Avalanche Photodiode Focal Plane
10 mm
Tier-1: 30V Back Illuminated APD Layer
Tier-2: 3.5V SOI CMOS Layer
Tier-3: 1.5V SOI CMOS Layer
Completed Pixel Cross-Sectional SEM
Transistors 3D
Via
VISA laser radar focal plane based on single-photon- sensitive Geiger-mode avalanche photodiodes
64 x 64 format
50-mm pixel size
To-Scale Pixel Layout of Completed 3-tier Laser Radar Focal Plane
Tier-3
High-Speed
Counter
Slide outlining the improved “resolution” of a 3D-integrated Ladar focal plane. The combined effect of the array size, the reduced pixel size, and the faster timing circuitry results in a ~80x improvement in voxel volume compared to previous designs. SEM cross-sectional photo of an 3D-integrated APS pixel on the upper right, and 3D CAD rendering (to-scale) of the 3D-integrated layout on the bottom of the slide.
Tier-2
APD
Drive/Sense
Circuitry
Tier-1
Avalanche
Photodiode
(APD)
~250 transistors/pixel
(50 mm x 50 mm)
Presented at 2006 ISSCC

36. First 3-D IC Multiproject Run (Three 180-nm, 1
First 3-D IC Multiproject Run (Three 180-nm, 1.5 volt FDSOI CMOS Tiers)
Leverages MIT-LL’s established 3D circuit integration technology
Low temperature oxide bonding, precision wafer-to-wafer overlay, high-density 3D interconnect
Preliminary 3D design kits developed
Mentor Graphics – MIT-LL, Cadence – NCSU, Thermal Models – CFRDC
Design guide release 11/04, fab start 6/05, 3D-integration complete 3/06
Completed 3DL1 Die Photo
Concepts being explored in run:
22 mm
3DL1 Participants (Industry, Universities, Laboratories)
Slide showing how MIT-LL is making the 3D integration process available to the research community through the first DARPA-sponsored 3D Multiproject Run.
This run will include 33 different designs from 21 different US organizations.
33 Designs

37. Cross-Section of 3-Tier 3D-integrated Circuit (DARPA 3DL1 Multiproject Run)
3 FDSOI CMOS Transistor Layers, 10-levels of Metal
Tier-1: 180-nm, 1.5V FDSOI CMOS
Tier-2: 180-nm
1.5V FDSOI CMOS
Tier-3: 180-nm, 1.5V FDSOI CMOS
Tier-3: Transistor Layer
Tier-2: Transistor Layer
3D-Via
3-Level Metal
Stacked
Vias
Oxide Bond Interface
10 mm
Tier-1: Transistor Layer
Back Metal
Metal Fill
Cross-sectional SEM of recently completed 3D Multiproject Run showing three FDSOI CMOS circuit layers stacked on top of each other and interconnected with 3D-vias.

38. 3D Technology Improvements (DARPA 3DL1 Multiproject Run)
High-Yield on >5000-link Scaled 3D-via Chains
3D technology enhancements successfully demonstrated in 3DL1 Run
Stacked 3D-vias for electrical and thermal interconnect
2X reduction in 3D-via size
Improved tier-to-tier overlay
5 mm
5 mm
Scaled
Conventional
Stack 3D-vias demonstrated
>95% yield on 4800 link chains
Stacked 3D-via resistance ~1W
Can be used as thermal vias
~0.5 mm 3s Tier-to-Tier Registration
A slide covering some of 3D technology improvements that were explored as part of the 3DL1 Multiproject Run including: stacked 3D vias for both electrical and thermal interconnect, scaled (1-um-diameter) 3D vias for tighter interconnect pitch, and 0.5 um 3 sigma overlay across fully processed 150-mm-diameter wafers.
99-Stage Ring
5 mm

39. 3-Tier, 3D-Integrated Ring Oscillator (DARPA 3DL1 Multiproject Run)
Functional 3-tier, 3D-integrated ring oscillator
Uses all three active transistor layers, 10 levels of metal and experimental stacked 3D-vias
Demonstrates viability of 3D integration process
Tier-1: FDSOI CMOS Layer
Tier-2: FDSOI CMOS Layer
Tier-3: FDSOI CMOS Layer
3D Ring Oscillator Cross-Sectional SEM
5 mm
Transistors 3D
Via
Stacked
3D Via
Stage Delay (ps)
Power Supply (V)
99-Stage Ring
3D ring oscillator test results from the 3DL1 Multiproject Run. This 99-stage circuit utilized active devices on all three tiers, all 10 levels of metal interconnect, and all 2D and 3D electrical vias (including the new stacked 3D-via test structure).

40. 3D IC Multiproject Run Highlights (a)
RPI, Jack McDonald (PI)
Designed high-bandwidth 3D SRAM for high-performance computing applications
Demonstrated first functional 3D-integrated, 3-tier memory
Stanford Univ., Sang-Min Lee, Bruce Wooley (PI)
Designed and demonstrated high dynamic range (18-19 bit) high frame rate (3000 fps) 3D ADC for LWIR focal plane array readouts
Reduced pixel size for complex readout to 50 mm x 50 mm
Slide showing some high-level overview results from the first DARPA-sponsored 3D Multiproject Run. This slide highlights the high-bandwidth 3-tier SRAM designed by RPI and a wide dynamic range A/D converter designed by Stanford.

41. 3D IC Multiproject Run Highlights (b) Post Process Released Resonator
UCLA, Frank Chang (PI)
Designed low power, low BER 10Gbps capacitor-coupled vertical Interconnects for 3D-IC
Demonstrated Baseband Impulse Shaping Interconnect (BISI) and self-synchronized RF Interconnect (RFI) at >11 GHz with BER < 1x10-14
>10x lower energy/bit and >3x faster than previously reported 180-nm 2D communication circuits
NRL-Cornell-BAE, Maxim Zalalutdinov (PI)
Designed 3D CMOS-integrated high frequency, high quality factor micromechanical resonators
Demonstrated tuning fork and slot resonators at 34MHz with Q = 4700
RFI 12.5 GHz data rate
Input vs Output
Output Eye diagram
Post Process Released Resonator
Slide showing some high-level overview results from the first DARPA-sponsored 3D Multiproject Run. This slide highlights the high-bandwidth, low power tier-to-tier interconnect circuit designed by UCLA and an integrated multi-tier MEMS, photodetector, readout circuit sensor designed by a team from NRL, Cornell, and BAE.

42. 3D IC Multiproject Run Highlights (c)
Cornell Univ., Sandip Tiwari (PI)
Designed full range of 3D test structures and circuits
Characterized 3D heat dissipation
Demonstrated functional asynchronous 3D FPGA
Demonstrated low voltage adaptive analog circuits with backgating
Demonstrated RF cross-talk reduction through 3D-integrated ground planes
Yale Univ., Eugenio Culurciello (PI)
Designed 3D integrated detector sensitive to intensity, contours, and motion
Demonstrated functionality of single and multiple tier photo detectors
Slide showing some high-level overview results from the first DARPA-sponsored 3D Multiproject Run. This slide highlights full range of 3D test structures designed by researchers at Cornell and a 3-tier photo detector designed by researchers at Yale.
Asynchronous 3D FPGA
3D pixel view
three 3D vias per pixel

43. Temperature Measurement Results from 3DL1 Multiproject Run
Thermal characterization structures included in 3DL1 Multiproject Run
Measure temperatures in stack
Explore thermal sink paths through buried oxide (BOX) vias and “Back-metal” hear sinks
Calibrate thermal modeling tools
3D Temperature Characterization Structure
Schematic cross-section of a thermal measurement test structure designed by MIT-LL and included in the 3DL1 run. The next few slides will show some of the measurement results from this thermal test device.

44. 3DM2 Multiproject Run (3 Active Tiers, 11 levels of Metal)
3DM2 includes 2 “digital” 180-nm FDSOI CMOS tiers and 1 RF 180-nm FDSOI CMOS tier
11 metal layers including:
2-mm-thick RF Backmetal
Tier-2 Backmetal
Second 3D Multiproject Design Schedule (3DM2)
3DM2 announcement (Mar 06)
Contributor selection (Apr 06)
Design guide release (Apr 06)
Submission deadline (November 06)
Schematic cross-section of the 3DM2 Darpa-sponsored Multiproject Run which completed it’s design phase in October and has just started fabrication. This 3-tier run will have two digital CMOS tiers and one RF CMOS tier.

45. 3D-Integration with III-V Detectors
150-mm-diameter InP wafer with oxide-bonded circuit layer transferred from silicon wafer
Enables extension of 3D-integration technology to higher density, longer wavelength focal plane detectors
Tight pixel-pitch IR focal planes and APD arrays
InGaAsP (1.06-mm), InGaAs (1.55-mm)
High-yield, 3.4 mm pitch 3D-via chains demonstrated
MIT-LL has begun to apply it’s 3-D integration technology to III-V, silicon CMOS integration. The photograph on the right shows a 150-mm-diameter InP wafer that has had a silicon circuit layer transferred on to it. The hope is to apply the 3D technology to these mixed material systems to enable large format, tight pixel pitch, infra red focal planes.
Presented at 2006 IPRM

46. Summary A Few Closing Remarks…
Transistor feasibility has been demonstrated to below ~10 nm gate lengths
“Conventional” CMOS (Bulk, SiO2 gate oxide, poly gates) faces significant challenges to scale below 45nm-node
Ultra-thin-body SOI, FinFET, Dual-Gate, Metal Gate, High-k
No new device technology has yet emerged that is expected to dethrone silicon CMOS
Moore’s Law scaling is showing its age and could run into serious speedbumps in the next few years (including economics), but the 2020 roadmap is theoretically feasible
Process technology improvements are no longer the performance drivers
Future performance improvements will most likely come through circuit, system architecture, and software advancements
Initial 3D technology demonstrations (at MIT-LL) are centered around advanced focal plane architectures
This is the “low hanging fruit”
Full impact of 3D integration is far from being realized, but has the potential of revolutionizing the design architecture of future circuits and systems
Potential application areas include: High-end focal planes, FPGAs, Dense memory, memory on processor, mixed signal systems, mixed material systems
Some closing comments on some of the issues with the 3D-integration approach, and what some of the potential application areas might be.