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ELEC 6270 Low power design of Electronic Circuits Advisor: Dr.Vishwani Agrawal Student: Chaitanya Bandi.

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Presentation on theme: "ELEC 6270 Low power design of Electronic Circuits Advisor: Dr.Vishwani Agrawal Student: Chaitanya Bandi."— Presentation transcript:

1 ELEC 6270 Low power design of Electronic Circuits Advisor: Dr.Vishwani Agrawal Student: Chaitanya Bandi

2 Index Ring Oscillator Operation Tools Used Schematic Power and Frequency Versus Voltage (Expected and Observed) for different values of N (where N is the number of gates). References

3 Ring Oscillator A ring oscillator is a device composed of an odd number of NOT gates whose output oscillates between two voltage levels, representing 1 and 0. The NOT gates, or inverters, are attached in a chain; the output of the last inverter is fed back into the first

4 Tools Used Design Architect: To create and Edit the Schematic Eldo: To find the Frequency of oscillations and Average Power consumed

5 Schematic from Design Architect Ringin: input pin to initialize the oscillations Ringout: output pin from at which oscillations are observed

6 Vdd= 5 v Vdd= 4v Simulation results of the Ring oscillator from ELDO for N=11

7 Vdd = 3 v Vdd=2v

8 Vdd= 1 v Vdd =.9 v

9 Vdd=.85v Vdd=.815

10 Rise time & Fall Time Vs Voltage Vdd (volts)Rise timefall time 50.08ns0.07ns 40.10ns0.07ns 30.11ns0.1ns 20.2ns0.1ns 10.8ns0.34ns 0.91.73n0.76ns 0.853.2ns0.82ns 0.8155.21ns1.83ns N=11 The rise times and fall times of the oscillator increases with a decrease in supply voltage which indicates that the delay of the gates increases with a decrease in the supply voltage.

11 For N=11, Power & Freq Vs Voltage Vdd (Volts)FrequencyPower 5826MHz3.382mW 4698MHz1.7mW 3562MHz702uW 2367MHz187uW 164.9MHz6uW 0.8519MHz1.18uW

12 For N=19, Power & Freq Vs Voltage Vdd (Volts)FrequencyPower 5826MHz6.61mW 4698MHz2.93mW 3562MHz1.212mW 2367MHz323uW 164.9MHz10.36uW 0.8519MHz2.038uW

13 For N=5, Power & Freq Vs Voltage Vdd(Volts)FrequencyPower 52.1GHz1.57mW 41.818GHz0.788mW 31.43GHz330uW 2.952GHz87uw 1168MHz2.89uW 0.8550MHz.54uW

14 N=19,11,5 Power Vs Voltage X-Axis: Voltage(Volts) Y-Axis: Power(uW)

15 N=19,11,5 Frequency Vs Voltage X-Axis: Voltage(Volts) Y-Axis: Frequency(MHz)

16 Power Vs number of gates(N) As the number of gates increases the Average power increases proportionally. X-axis: Number of gates Y-axis: Average Power

17 Expected Power and Frequency 1)Power α f* (Vdd) ^2 ; where f is the observed frequency 2) Delay of Each gate α (Vdd)/(Vdd-Vth) Vth = 0.54v for tsmc035 technology

18 Average power & Expected Power N=11 Vdd(volts)average powerExpected Power 53.414mW 41.718mW 1.845mW 3.711mW 0.846mW 2.191mW 0.246.5mW 16.33uW 10.67uW 0.851.173uW 2.322uW 0.65.2nW 11.5nW

19 Average power & Expected Power N=19 Vdd(volts)Average PowerExpected Power 56.61mW 42.93mW 3.600mW 31.212mW 1.571mW 2323uW 466.52uW 110.36uW 20.43uW 0.852.038uW 4.37uW

20 Average power & Expected Power N=5 Vdd(volts)Average PowerExpected Power 51.57mW 40.788mW 1.087mW 3330uW 645.54uW 287uw 284.69uW 12.89uW 25.12uW 0.85.54uW 6.33uw

21 Observed & Expected Frequency N=11 VDD (Volts)frequencyExpected Frequency 51.389GHz- 41.176GHz1.34Ghz 30.956GHz1.277Ghz 2.627GHz1.136Ghz 1.109GHz.716GHz 0.85.0327GHz.568GHz 0.60.326MHz.155GHz

22 Observed & Expected Frequency N=19 Vdd(Volts)FreqExpected Freq 5826MHz 4698MHz800.9MHz 3562MHz759.3MHz 2367MHz675.8MHz 164.9MHz425.9MHz 0.8519MHz337.7MHz

23 Observed & Expected Frequency N=5 VDD(volts)FreqExpected Freq 52.1GHz 41.818GHz2.036GHz 31.43GHz1.93GHz 2.952Ghz1.718GHz 1168MHz1.08GHz 0.8550MHz858MHz

24 Observations If the Vdd is changed from 5v to 0.85V there is a power reduction of about 99.9%, but the frequency of oscillations is decreased by 76%. The Frequency of oscillations decreases as the number of gates in the oscillator increases. The Power consumption increases in proportion to the number of gates in the oscillator. The Observed frequencies are lesser than the expected frequencies due to large delays in the gates at low operating voltages.

25 References: 1.Fall 2007: ELEC6270 Low Power Design Electronics Class Slides from Dr. Agrawal 2.Fall 2007: ELEC6250 Computer Aided Design of Digital Logic Circuits Lectures 4,23 from Dr. Nelson’s Class slides. 3.http://www.iue.tuwien.ac.at/phd/martins/node46.html

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