1. Copyright 2000 Cadence Design Systems. Permission is granted to reproduce without modification. Conclusion Summary Research trends Resources

2. Copyright 2000 Cadence Design Systems. Permission is granted to reproduce without modification. Summary Most FV research tries to address the following issues: –Automation –Expressiveness –Scalability As we have seen, there are tradeoffs among these goals...

3. Copyright 2000 Cadence Design Systems. Permission is granted to reproduce without modification. Automation v. expressiveness This tradeoff is made differently by: –Model checking/temporal logic temporal, finite state –Symbolic simulation non-temporal, but higher capacity –First-order decision procedures non-temporal, infinite state Only model checking can use reachability. The other two require user invariants.

4. Copyright 2000 Cadence Design Systems. Permission is granted to reproduce without modification. Automation: heuristic methods Symbolic model checking (BDDs) –partitioned T/Rs, early quantification –search order heuristics –variable ordering Other methods –symmetry reductions [ID96] –partial order methods (see SPIN) Current research topics: –frontier partitioning and search order [FKZ+00] –using SAT algorithms [ABE00] –efficient LTL tableau procedures [SB00]

5. Copyright 2000 Cadence Design Systems. Permission is granted to reproduce without modification. Automation: debugging methods Various incomplete search methods Current research areas: –using SAT for bounded counterexamples [BCCZ99] –using underapproximations [RS95]

6. Copyright 2000 Cadence Design Systems. Permission is granted to reproduce without modification. Expressiveness: infinite state Hybrid/ real time systems [AHH96] –Include some continuous variables Predicate abstraction [GS97] –Use decision procedures in model checking –Provides a stronger abstraction of T/R Regular state transducers [BJNT00] –Handles infinitely many processes –Does not always converge Lossy queue systems [AJ96] –A decidable special case

7. Copyright 2000 Cadence Design Systems. Permission is granted to reproduce without modification. Scalability: proof decomposition Generally at the expense of automation Current research areas: –TP based on model checking [McM99b] –TP based on symbolic simulation [AJS98] –TP based on decision procedures [SH99] Combining these methods is also a promising area (or, e.g., combining CMC and predicate abstraction).

8. Copyright 2000 Cadence Design Systems. Permission is granted to reproduce without modification. Model checking resources SPIN (Bell Labs) –features sequential language LTL model checking explicit-state, with state-space reductions –typical applications telecom protocols –URL: http://netlib.bell-labs.com/netlib/spin/whatispin.html

9. Copyright 2000 Cadence Design Systems. Permission is granted to reproduce without modification. MC resources, cont. Muphi (Stanford) –features explicit-state search reductions based on symmetry –typical applications abstract cache coherence protocols –URL: http://sprout.stanford.edu/dill/murphi.html

10. Copyright 2000 Cadence Design Systems. Permission is granted to reproduce without modification. MC resources, cont. VIS (CU/UCB) –features symbolic CTL model checking many BDD optimizations verilog input –typical applications hardware verification –URL: http://vlsi.colorado.edu/~vis/w

11. Copyright 2000 Cadence Design Systems. Permission is granted to reproduce without modification. Compositional MC resources SMV (Cadence) –features BDD based LTL/CTL model checking HDL-like language (and verilog) Proof assistant for compositional verification –typical applications hardware verification refinement of protocols to RTL level –URL: http://www-cad.eecs.berkeley.edu/~kenmcmil/smv

12. Copyright 2000 Cadence Design Systems. Permission is granted to reproduce without modification. Compositional MC, cont. Mocha (UCB) –features support for modular verification compositional rules –typical applications hardware verification cache protocols –URL: http://www- cad.eecs.berkeley.edu/Respep/Research/mocha/

13. Copyright 2000 Cadence Design Systems. Permission is granted to reproduce without modification. Theorem proving resources PVS (SRI) –features higher order logic prover integrated decision procedures –typical applications microcode verification Goëdels theorems (!) –URL: http://pvs.csl.sri.com/