1. Scaling of High Frequency III-V Transistors rodwell@ece.ucsb.edu 805-893-3244, 805-893-5705 fax Short Course, 2009 Conference on InP and Related Materials, Newport Beach, CA, May 10-14 Mark Rodwell University of California, Santa Barbara

2. THz Transistors Transistor bandwidths are increasing rapidly. Si MOSFETs will soon reach 500+ GHz cutoff frequencies. It is now clear III-V bipolar transistors can reach ~2-3 THz cutoff frequencies. III-V FETs have comparable potential, but the prospects and analysis are less clear. The limits to transistor bandwidth are: contact resistivities gate dielectric capacitance densities. device and IC power density & thermal resistance. challenges in reliably fabricating small devices.

3. Why THz Transistors ?

4. Why Build THz Transistors ? THz amplifiers→ THz radios → imaging, sensing, communications precision analog design at microwave frequencies → high-performance receivers 500 GHz digital logic → fiber optics Higher-Resolution Microwave ADCs, DACs, DDSs

5. Performance Figures of Merit

6. Transistor figures of Merit / Cutoff Frequencies H 21 =short-circuit current gain gains, dB MAG = maximum available power gain: impedance-matched U= unilateral power gain: feedback nulled, impedance-matched f max power-gain cutoff frequency f  current-gain cutoff frequency

7. What Determines Gate Delay ?

8. HBT Design For Digital & Mixed-Signal Performance from charge-control analysis: analog ICs have similar bandwidth constraints...

9. High-Frequency Electron Device Design

10. Simple Device Physics: Resistance Good approximation for contact widths less than 2 transfer lengths. bulk resistancecontact resistance -perpendicular contact resistance - parallel

11. Simple Device Physics: Depletion Layers capacitancetransit timespace-charge limited current

12. Simple Device Physics: Thermal Resistance Exact Carslaw & Jaeger 1959 Long, Narrow Stripe HBT Emitter, FET Gate Square ( L by L ) IC on heat sink

13. Simple Device Physics: Fringing Capacitance wiring capacitanceFET parasitic capacitances VLSI power-delay limits FET scaling constraints

14. Electron Plasma Resonance: Not a Dominant Limit

18. Frequency Limits and Scaling Laws of (most) Electron Devices To double bandwidth, reduce thicknesses 2:1Improve contacts 4:1 reduce width 4:1, keep constant length increase current density 4:1 PIN photodiode

19. parameterchange collector depletion layer thicknessdecrease 2:1 base thicknessdecrease 1.414:1 emitter junction widthdecrease 4:1 collector junction widthdecrease 4:1 emitter contact resistancedecrease 4:1 current densityincrease 4:1 base contact resistivitydecrease 4:1 Changes required to double transistor bandwidth: Linewidths scale as the inverse square of bandwidth because thermal constraints dominate. Bipolar Transistor Scaling Laws

20. parameterchange gate lengthdecrease 2:1 gate dielectric capacitance densityincrease 2:1 gate dielectric equivalent thicknessdecrease 2:1 channel electron densityincrease 2:1 source & drain contact resistancedecrease 4:1 current density (mA/  m) increase 2:1 Changes required to double transistor bandwidth: Linewidths scale as the inverse of bandwidth because fringing capacitance does not scale. FET Scaling Laws

21. THz & nm Transistors: it's all about the interfaces Metal-semiconductor interfaces (Ohmic contacts): very low resistivity Dielectric-semiconductor interfaces (Gate dielectrics): very high capacitance density Transistor & IC thermal resistivity.

22. Bipolar Transistors

23. Indium Phosphide Heterojunction Bipolar Transistors Z. Griffith E. Lind

24. Bipolar Transistor Operation

25. Transistor Hybrid-Pi equivalent circuit model

26. Cutoff frequencies in HBTs

27. Epitaxial Layer Structure

28. emitter emitter cap graded base collector subcollector Epitaxy: InP Emitter, InGaAs Base, InP Collector, Both Junctions Graded Key Features: N++ InGaAs emitter contact layer InP emitter InGaAs/InAlAs superlattice e/b grade InGaAs graded base bandgap or doping grade BC setback layer InGaAs/InAlAs superlattice b/c grade InP collector InGaAs etch-stop layer thin for heat conduction InP subcollector M. Dahlstrom Z. Griffith UCSB M. Urteaga TSC

29. emitter emitter cap graded base collector subcollector Epitaxy with Abrupt BE Junction Similar design Abrupt E/B junction (no e/b grade) Advantages: ease of stopping emitter etch on base → good base contacts Disadvantages: Increased V be. Cannot make e/b ledge. M. Dahlstrom Z. Griffith E. Lind

30. Alternative Grades for Thinner Epitaxy Common Grade in Literature InGaAs/InAlAs 18 nm thick, 1.5 nm period Sub-monolayer Grade 0.15 nm InAlAs, (0.15 to 0.165 nm InGaAs) 10.8 nm thick Strained In x Ga 1-x As Grade InGaAs/GaAs 6 nm E. Lind Z. Griffith

31. Other Methods of Grading the Junctions IEDM 2001 InGaAs/InGaAsP/InP gradeInP/GaAsSb/InP DHBT -suitable for MOCVD growth - excellent results - does not need B/C grading - E/B band alignment through GaAsSb alloy ratio (strain) or InAlAs emitter

32. Transport Analysis

33. Approximate Carrier Transit Times

34. Base Transit Time with Graded Base Dino Mensa

35. Base Transit Time: Grading Approaches Dino Mensa Miguel Urteaga Mattias Dahlström Compositional grading: strained graded InGaAs base Doping grading unstrained In 0.53 Ga 0.47 As base

36. Collector Transit Time T. Ishibashi

37. Space-Charge Limited Current Density → C cb charging time Collector Field Collapse (Kirk Effect) Collector Depletion Layer Collapse Collector capacitance charging time scales linearly with collector thickness if J = J max

38. Space-Charge-Limited Current (Kirk effect) in DHBTs

39. Current-induced Collector Velocity Overshoot J=0 J= 8 mA/um 2 300 Å InGaAs base 2000 Å InP collector 280 GHz peak f  Nakajima, H. "A generalized expression for collector transit time of HBTs taking account of electron velocity modulation," Japanese Journal of Applied Physics, vo. 36, Feb. 1997, pp. 667-668 T. Ishibashi

40. Transit time Modulation Causes C cb Modulation Camnitz and Moll, Betser & Ritter, D. Root

41. Emitter-Base Junction Effects Electron degeneracy contributes 1  - μm 2 equivalent series resistance Space-charge storage need thin layer to avoid substantial charge storage delays Voltage drops in depletion region need thin layer & high electron density Rodwell Lundstrom.

42. RC parasitics

43. Simple Device Physics: Resistance Good approximation for contact widths less than 2 transfer lengths. bulk resistancecontact resistance -perpendicular contact resistance - parallel

44. HBT RC Parasitics base contact width < 2 transfer lengths → simple analysis Limiting case of Pulfrey / Vaidyanathan f max model.

45. HBT RC Parasitics

46. Base-Collector Time Constant & Fmax.

47. Relationship to Equivalent Circuit Model

48. Device Design Device Scaling

49. Simple Device Physics: Thermal Resistance Exact Carslaw & Jaeger 1959 Long, Narrow Stripe HBT Emitter, FET Gate Square ( L by L ) IC on heat sink

50. Bipolar Transistor Design

51. Bipolar Transistor Design: Scaling

52. parameterchange collector depletion layer thicknessdecrease 2:1 base thicknessdecrease 1.414:1 emitter junction widthdecrease 4:1 collector junction widthdecrease 4:1 emitter contact resistancedecrease 4:1 current densityincrease 4:1 base contact resistivitydecrease 4:1 Changes required to double transistor bandwidth: Linewidths scale as the inverse square of bandwidth because thermal constraints dominate. Bipolar Transistor Scaling Laws

53. Thermal Resistance Scaling : Transistor, Substrate, Package

54. Probable best solution: Thermal Vias ~500 nm below InP subcollector...over full active IC area.

55. InP Bipolar Transistor Scaling Roadmap emitter5122561286432 nm width 16 8421  m 2 access  base300 1751206030 nm contact width, 20 1052.51.25  m 2 contact  collector150 106755337.5 nm thick, 4.5 9183672 mA/  m 2 current density 4.9 43.32.752-2.5 V, breakdown f  370520 73010001400 GHz f max 490 850 130020002800 GHz power amplifiers 245 430 66010001400 GHz digital 2:1 divider 150 240 330480660 GHz industryuniversity →industry university 2007-8 appears feasible maybe

56. Can we make a 1 THz SiGe Bipolar Transistor ? InPSiGe emitter6418nm width 2 1.2  m 2 access  base6456nm contact width, 2.5 1.4  m 2 contact  collector53 15 nm thick 36125mA/  m 2 2.75 ??? V, breakdown f  10001000 GHz f max 20002000 GHz PAs10001000 GHz digital480480GHz (2:1 static divider metric) Assumes collector junction 3:1 wider than emitter. Assumes SiGe contacts 2:1 wider than junctions Simple physics clearly drives scaling transit times, C cb /I c → thinner layers, higher current density high power density → narrow junctions small junctions→ low resistance contacts Key challenge: Breakdown 15 nm collector → very low breakdown (also need better Ohmic contacts)

57. HBT Design For Digital & Mixed-Signal Performance from charge-control analysis:

58. InP HBT: Status

59. InP DHBTs: September 2008 250 nm 600nm 350 nm 250 nm 125 nm

60. 512 nm InP DHBT Production DDS IC: 4500 HBTs20-40 GHz op-amps 500 nm mesa HBT 150 GHz M/S latches175 GHz amplifiers Laboratory Technology Teledyne / BAETeledyne / UCSB UCSBUCSB / Teledyne / GCS 500 nm sidewall HBT f  = 405 GHz f max = 392 GHz V br, ceo = 4 V Teledyne 20 GHz clock 53-56 dBm OIP3 @ 2 GHz with 1 W dissipation ( Teledyne ) Z. Griffith M. Urteaga P. Rowell D. Pierson B. Brar V. Paidi

61. 256 nm Generation InP DHBT 150 nm thick collector 70 nm thick collector 60 nm thick collector 200 GHz master-slave latch design Z. Griffith, E. Lind J. Hacker, M. Jones 324 GHz Amplifier

62. 324 GHz Medium Power Amplifiers in 256 nm HBT ICs designed by Jon Hacker / Teledyne Teledyne 256 nm process flow- Hacker et al, 2008 IEEE MTT-S ~2 mW saturated output power

63. 128 / 64 / 32 nm HBT Technologies

64. Conventional ex-situ contacts are a mess textbook contact with surface oxide Interface barrier → resistance Further intermixing during high-current operation → degradation with metal penetration THz transistor bandwidths: very low-resistivity contacts are required

65. Improvements in Ohmic Contacts 128 nm generation requires ~ 4  - μm 2 emitter & base resistivities 64 nm generation requires ~ 2  - μm 2 Contacts to N-InGaAs*: Mo MBE in-situ 2.2 (+/- 0.5)  - μm 2 TiW ex-situ / NH4 pre-clean ~2.2  - μm 2 variable between process runs Contacts to P-InGaAs: Mo MBE in-situ below 2.5  - μm 2 Pd/Ti...ex-situ ~4  - μm 2...far better contacts coming... *measured emitter resistance remains higher than that of contacts. A.. Crook V. Jain A. Barakshar M. Wistey U. Singisetti S. Bank

66. Mo Emitter Contacts: Robust Integration into Process Flow Proposed Process Integration: M. Wistey A. Barakshar U. Singisettti V. Jain

67. Process Must Change Greatly for 128 / 64 / 32 nm Nodes Undercutting of emitter ends control undercut → thinner emitter thinner emitter → thinner base metal thinner base metal → excess base metal resistance {101}A planes: fast {111}A planes: slow

68. 128 nm Emitter Process: Dry Etched Metal & Semiconductor Litho pattern metal sidewalldry etchwet etch results @ c.a. 200 nm emitter metal width E. Lind

69. Planarization E/B Processes for 64 & 32 nm Planarization boundary E; Lobisser V. Jain G. Burek

70. III-V FET Scaling

71. Simple FET Scaling Goal double transistor bandwidth when used in any circuit → reduce 2:1 all capacitances and all transport delays → keep constant all resistances, voltages, currents All lengths, widths, thicknesses reduced 2:1 S/D contact resistivity reduced 4:1 If T ox cannot scale with gate length, C parasitic / C gs increases, g m / W g does not increase hence C parasitic /g m does not scale

72. FET scaling: Output Conductance & DIBL transconductance → Keep L g / T ox constant as we scale L g output conductance

73. parameterchange gate lengthdecrease 2:1 gate dielectric capacitance densityincrease 2:1 gate dielectric equivalent thicknessdecrease 2:1 channel electron densityincrease 2:1 source & drain contact resistancedecrease 4:1 current density (mA/  m) increase 2:1 Changes required to double transistor bandwidth: FET Scaling Laws

74. III-V MOSFETs for VLSI What is it ? MOSFET with an InGaAs channel What are the problems ? low electron effective mass→ constraints on scaling ! must grow high-K on InGaAs, must grow InGaAs on Si Our focus today is III-V FET scaling generally Why do it ? low electron effective mass→ higher electron velocity more current, less charge at a given insulator thickness & gate length very low access resistance

75. Low Effective Mass Impairs Vertical Scaling Shallow electron distribution needed for high g m / G ds ratio. Only one vertical state in well. Minimum ~ 5 nm well thickness. → constrains gate length scaling. For thin wells, only 1st state can be populated. For very thin wells, 1st state approaches L-valley. Energy of L th well state

76. Density-Of-States Capacitance Two implications: - With N s >10 13 /cm 2, electrons populate satellite valleys - Transconductance limited by finite state density and n is the # of band minima Fischetti et al, IEDM2007 Solomon & Laux, IEDM2001

77. Drive Current in the Ballistic & Degenerate Limits n = # band minima c dos,o = density of states capacitance for m*=m o & n=1 Error bars on Si data points correct for (E f -E c )>> kT approximation

78. HEMT Scaling Challenge: Low Gate Barrier Tunneling through barrier → sets minimum thickness SourceDrain Gate Gate barrier is low: ~0.6 eV Emission over barrier → limits 2D carrier density K Shinohara

79. HEMT Scaling Challenge: High Access Resistance low leakage: need high barrier under gate SourceDrain Gate Gate barrier also lies under source / drain contacts low resistance: need low barrier under contacts widegap barrier layer N+ layer K Shinohara

80. THz III-V FET Scaling: What Must Be Done As gate length is reduced... channel thickness should be reduced... barrier thickness should be reduced... target g m /W g and I d /W g should be increased... source and drain access resistivity should be reduced... We face serious difficulties in doing these.

81. A MOSFET Might Scale Better than a HEMT no gate barrier under S/D contacts high-K gate barrier Overlap between gate and N+ source/drain

82. Interconnects

83. kzkz Parasitic slot mode -V0V+V 0V Coplanar Waveguide No ground vias No need (???) to thin substrate Parasitic microstrip mode +V 0V Hard to ground IC to package substrate mode coupling or substrate losses ground plane breaks → loss of ground integrity Repairing ground plane with ground straps is effective only in simple ICs In more complex CPW ICs, ground plane rapidly vanishes → common-lead inductance → strong circuit-circuit coupling 40 Gb/s differential TWA modulator driver note CPW lines, fragmented ground plane 35 GHz master-slave latch in CPW note fragmented ground plane 175 GHz tuned amplifier in CPW note fragmented ground plane poor ground integrity loss of impedance control ground bounce coupling, EMI, oscillation III-V: semi-insulating substrate→ substrate mode coupling Silicon conducting substrate → substrate conductivity losses

84. kzkz Classic Substrate Microstrip Strong coupling when substrate approaches ~ d / 4 thickness H W Thick Substrate → low skin loss Zero ground inductance in package High via inductance 12 pH for 100  m substrate -- 7.5  @ 100 GHz TM substrate mode coupling Line spacings must be ~3*(substrate thickness) lines must be widely spaced ground vias must be widely spaced all factors require very thin substrates for >100 GHz ICs → lapping to ~50  m substrate thickness typical for 100+ GHz No ground plane breaks in IC

85. fewer breaks in ground plane than CPW III-V MIMIC Interconnects -- Thin-Film Microstrip narrow line spacing → IC density... but ground breaks at device placements still have problem with package grounding thin dielectrics → narrow lines → high line losses → low current capability → no high-Z o lines H W...need to flip-chip bond no substrate radiation, no substrate losses InP mm-wave PA (Rockwell)

86. No breaks in ground plane III-V MIMIC Interconnects -- Inverted Thin-Film Microstrip narrow line spacing → IC density... no ground breaks at device placements still have problem with package grounding thin dielectrics → narrow lines → high line losses → low current capability → no high-Z o lines...need to flip-chip bond Some substrate radiation / substrate losses InP 150 GHz master-slave latch InP 8 GHz clock rate delta-sigma ADC

87. No clean ground return ? → interconnects can't be modeled ! 35 GHz static divider interconnects have no clear local ground return interconnect inductance is non-local interconnect inductance has no compact model InP 8 GHz clock rate delta-sigma ADC 8 GHz clock-rate delta-sigma ADC thin-film microstrip wiring every interconnect can be modeled as microstrip some interconnects are terminated in their Zo some interconnects are not terminated...but ALL are precisely modeled

88. VLSI Interconnects with Ground Integrity & Controlled Z o negligible breaks in ground plane narrow line spacing → IC density negligible ground breaks @ device placements still have problem with package grounding thin dielectrics → narrow lines → high line losses → low current capability → no high-Z o lines...need to flip-chip bond no substrate radiation, no substrate losses

89. Conclusions

90. Few-THz Transistors Scaling limits: contact resistivities, device and IC thermal resistances. Few-THz InP Bipolar Transistors: can it be done ? 62 nm (1 THz f , 1.5 THz f max ) scaling generation is feasible. 700 GHz amplifiers, 450 GHz digital logic Is the 32 nm (1 THz amplifiers) generation feasible ? Few-THz InP Field-Effect Transistors: can it be done? challenges are gate barrier, vertical scaling, source/drain access resistance, increased gm and drive current. 2DEG carrier concentrations must increase. S/D regrowth offers a path to lower access resistance. Solutions needed for gate barrier: maybe even MOSFET ?

91. What Would We Do With Them ? THz amplifiers→ THz radios → imaging, sensing, communications precision analog design at microwave frequencies → high-performance receivers 500 GHz digital logic → fiber optics Higher-Resolution Microwave ADCs, DACs, DDSs