1. Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 30: November 12, 2014 Memory Core: Part 2

2. Today Multiport SRAM DRAM Penn ESE370 Fall2014 -- DeHon 2

3. Memory Bank Penn ESE370 Fall2014 -- DeHon 3

4. Multiport RAM Penn ESE370 Fall2014 -- DeHon 4

5. Mulitport Perform multiple operations simultaneously –E.g. Processor register file add r1,r2,r3 R3  R1+R2 Requires two reads and one write Penn ESE370 Fall2014 -- DeHon 5

6. Simple Idea Add access transistors to 5T Penn ESE370 Fall2014 -- DeHon 6

7. Watch? What do we need to be careful about? Penn ESE370 Fall2014 -- DeHon 7

8. Adding Write Port Penn ESE370 Fall2014 -- DeHon 8

9. Write Port What options does this raise? Penn ESE370 Fall2014 -- DeHon 9

10. Opportunity Asymmetric cell size Separate sizing constraints –Weak drive into write port (W restore ) –Strong drive into read port (W buf ) Penn ESE370 Fall2014 -- DeHon 10

11. Multiple Read Ports What if want more than two read ports? Can we do this again? Penn ESE370 Fall2014 -- DeHon 11

12. Robust Read What makes more robust? Sizing impact? Penn ESE370 Fall2014 -- DeHon 12

13. Isolate BL form Mem How make this work? Sizing impact? Penn ESE370 Fall2014 -- DeHon 13

14. Isolate BL form Mem Penn ESE370 Fall2014 -- DeHon 14 Larger, but more robust Essential for large # of read ports Precharge ReadData High

15. Multiple Write Ports How about multiple write ports? –Assuming at most one write per word Penn ESE370 Fall2014 -- DeHon 15

16. Multiple Write Ports Penn ESE370 Fall2014 -- DeHon 16

17. DRAM Penn ESE370 Fall2014 -- DeHon 17

18. Penn ESE370 Fall2014 -- DeHon 18 Some Numbers (memory) Register as stand-alone element (14T)  4K 2 Static RAM cell (6T)  1K 2 –SRAM Memory (single ported) Dynamic RAM cell (DRAM process)  100 2 Dynamic RAM cell (SRAM process)  300 2

19. 1T 1C DRAM Simplest case – Memory is capacitor –Feature of DRAM process is ability to make large capacitor compactly Penn ESE370 Fall2014 -- DeHon 19

20. DRAM Capacitors Sunami, Solid State Circuit, January 2008 Penn ESE370 Fall2014 -- DeHon 20 http://www.ieee.org/portal/site/sscs/menuitem.f07ee9e3b2a01d06bb9305765bac26c8/index.jsp?&pName=sscs_level1_article&TheCat=2171&path=sscs/08Winter&file=Sunami.xml

21. DRAM Trench Capacitor Sunami, Solid State Circuit, January 2008 Penn ESE370 Fall2014 -- DeHon 21 http://www.ieee.org/portal/site/sscs/menuitem.f07ee9e3b2a01d06bb9305765bac26c8/index.jsp?&pName=sscs_level1_article&TheCat=2171&path=sscs/08Winter&file=Sunami.xml

22. DRAM Capacitance Scaling Sunami, Solid State Circuit, January 2008 Penn ESE370 Fall2014 -- DeHon 22 http://www.ieee.org/portal/site/sscs/menuitem.f07ee9e3b2a01d06bb9305765bac26c8/index.jsp?&pName=sscs_level1_article&TheCat=2171&path=sscs/08Winter&file=Sunami.xml

23. 1T DRAM What happens when read this cell? Penn ESE370 Fall2013 -- DeHon 23 Cbit << Cbl

24. 1T DRAM On read, charge sharing –V BL = (C bit /C BL )V store Small swing on bit line –Must be able to detect –Means want large C bit limit bits/bitline so V BL large enough Cell always depleted on read –Must be rewritten Penn ESE370 Fall2013 -- DeHon 24

25. Penn ESE370 Fall2013 -- DeHon 25 Dynamic RAM Takes sharing idea one step further Share refresh/restoration logic as well Only left with access transistor and capacitor

26. 3T DRAM Penn ESE370 Fall2014 -- DeHon 26

27. 3T DRAM How does this work? –Write? –Read? Penn ESE370 Fall2014 -- DeHon 27

28. 3T DRAM Correct operation not sensitive to sizing Does not deplete cell on read No charge sharing with stored state All NMOS (single well) Precharge ReadData Must use V dd +V TN on W to write full voltage Penn ESE370 Fall2014 -- DeHon 28

29. Energy (if time permits) Penn ESE370 Fall2014 -- DeHon 29

30. Single Port Memory What fraction is involved in a read/write? What are most cells doing on a cycle? Reads are slow –Cycles long  lots of time to leak Penn ESE370 Fall2014 -- DeHon 30

31. ITRS 2009 45nm Penn ESE370 Fall2014 -- DeHon 31 High Performance Low Power I sd,leak 100nA/  m50pA/  m I sd,sat 1200  A/  m560  A/  m C g,total 1fF/  m0.91fF/  m V th 285mV585mV C 0 = 0.045  m × C g,total

32. High Power Process V=1V d=1000  =0.5 W access =W buf =2 Full swing for simplicity C sc = 0 –(just for simplicity, typically <C load ) BL: C load =1000C 0 ≈ 45 fF = 45×10 -15 F W N = 2  I leak = 9×10 -9 A P= (45×10 -15 ) freq + 1000×9×10 -9 W Penn ESE370 Fall2014 -- DeHon 32

33. Relative Power P= (45×10 -15 ) freq + 1000×9×10 -9 W P= (4.5×10 -14 ) freq + 9×10 -6 W Crossover freq<200MHz How partial swing on bit line change?  Reduce dynamic energy  Increase percentage in leakage energy  Reduce crossover frequency Penn ESE370 Fall2014 -- DeHon 33

34. Consequence Leakage energy can dominate in large memories Care about low operating (or stand-by) power Use process or transistors with high V th –Reduce leakage at expense of speed Penn ESE370 Fall2014 -- DeHon 34

35. Idea Memory can be compact Rich design space Demands careful sizing Penn ESE370 Fall2014 -- DeHon 35

36. Admin Project 2 out –Milestone due Tuesday Friday here for Memory Periphery Monday in Detkin Penn ESE370 Fall2014 -- DeHon 36