1. Low Density Parity Check (LDPC) Code Implementation Matthew Pregara & Zachary Saigh Advisors: Dr. In Soo Ahn & Dr. Yufeng Lu Dept. of Electrical and Computer Eng.

2. 2 Contents  Background and Motivation  Linear Block Coding Example  Hard Decision Tanner Graph Decoding  Constructing LDPC Codes  Soft Decision Decoding  Results  Conclusion

3. 3 Background  ARQ: Automatic Repeat Request  Detects errors and requests retransmission  Example: Even or Odd Parity  FEC: Forward Error Correction  Detects AND Corrects Errors  Examples:  Linear Block Coding  Turbo Codes  Convolutional Codes

4. Why LDPC?  Low decoding complexity  Higher code rate  Better Error performance  Industry standard for:  802.11n Wi-Fi  Digital Video Broadcasting  WiMAX and 4G 4

5. Performance Comparison 5 (taken from [1])

6. Project Goals  Create LDPC code system simulation with MATLAB/Simulink  Implement a scaled down LDPC system on a FPGA using Xilinx System Generator  Complete System performance comparison between MATLAB/Simulink and FPGA implementation 6

7. 7 Linear Block Coding  Block Codes are denoted by (n, k).  k = message bits (message word)  n = message bits + parity bits (coded bits)  # of parity bits: m = n - k  Code Rate R = k/n  Ex: (7,4) code  4 message bits  +3 parity bits  = 7 coded bits  Code rate R = 4/7

8. 8 Hamming Code Example

9. 9 Constructing Hamming Code  Factor x n +1  Populate G matrix (k x n) with shifted factor  Take reduced row echelon form to find Systematic G matrix from G matrix  H matrix is obtained by manipulating the systematic G matrix.

10. 10 Encoding Example

11. 11 Decoding  S = rcvd. code word × H T

12. 12 Correcting Errors  In this case the 2 nd bit is corrupted  Invert the corrupted bit according to the location found by the syndrome table

13. 13 Tanner Graph and Hard Decision Decoding (2458) (1236) (3678) (1457) (8,4) Example

14. 14 Hard Decision Decoding Check Nodes Activities C1C1 ReceiveV 2 → 1V 4 → 1V 5 → 0V 8 → 1 Send0 → V 2 0 → V 4 1 → V 5 0 → V 8 C2C2 ReceiveV 1 → 1V 2 → 1V 3 → 0V 6 → 1 Send0 → V 1 0 → V 2 1 → V 3 0 → V 6 C3C3 ReceiveV 3 → 0V 6 → 1V 7 → 0V 8 → 1 Send0 → V 3 1 → V 6 0 → V 7 1 → V 8 C4C4 ReceiveV 1 → 1V 4 → 1V 5 → 0V 7 → 0 Send1 → V 1 1 → V 4 0 → V 5 0 → V 7

15. 15 Hard Decision Decoding Check Nodes Activities C1C1 ReceiveV 2 → 1V 4 → 1V 5 → 0V 8 → 1 Send0 → V 2 0 → V 4 1 → V 5 0 → V 8 C2C2 ReceiveV 1 → 1V 2 → 1V 3 → 0V 6 → 1 Send0 → V 1 0 → V 2 1 → V 3 0 → V 6 C3C3 ReceiveV 3 → 0V 6 → 1V 7 → 0V 8 → 1 Send0 → V 3 1 → V 6 0 → V 7 1 → V 8 C4C4 ReceiveV 1 → 1V 4 → 1V 5 → 0V 7 → 0 Send1 → V 1 1 → V 4 0 → V 5 0 → V 7 Update

16. 16 Hard Decision Decoding Check Nodes Activities C1C1 ReceiveV 2 → 1V 4 → 1V 5 → 0V 8 → 1 Send0 → V 2 0 → V 4 1 → V 5 0 → V 8 C2C2 ReceiveV 1 → 1V 2 → 1V 3 → 0V 6 → 1 Send0 → V 1 0 → V 2 1 → V 3 0 → V 6 C3C3 ReceiveV 3 → 0V 6 → 1V 7 → 0V 8 → 1 Send0 → V 3 1 → V 6 0 → V 7 1 → V 8 C4C4 ReceiveV 1 → 1V 4 → 1V 5 → 0V 7 → 0 Send1 → V 1 1 → V 4 0 → V 5 0 → V 7 Update

17. 17 Hard Decision Decoding Check Nodes Activities C1C1 ReceiveV 2 → 1V 4 → 1V 5 → 0V 8 → 1 Send0 → V 2 0 → V 4 1 → V 5 0 → V 8 C2C2 ReceiveV 1 → 1V 2 → 1V 3 → 0V 6 → 1 Send0 → V 1 0 → V 2 1 → V 3 0 → V 6 C3C3 ReceiveV 3 → 0V 6 → 1V 7 → 0V 8 → 1 Send0 → V 3 1 → V 6 0 → V 7 1 → V 8 C4C4 ReceiveV 1 → 1V 4 → 1V 5 → 0V 7 → 0 Send1 → V 1 1 → V 4 0 → V 5 0 → V 7 Update

18. 18 Variable Node Decisions Variable Nodesyiyi Messages from Check NodesDecision V1V1 1C 2 → 0C 4 → 11 V2V2 1C 1 → 0C 2 → 00 V3V3 0C 2 → 1C 3 → 00 V4V4 1C 1 → 0C 4 → 11 V5V5 0C 1 → 1C 4 → 00 V6V6 1C 2 → 0C 3 → 11 V7V7 0C 3 → 0C 4 → 00 V8V8 1C 1 → 0C 3 → 11

19. 19 Differences of LDPC Code  Construct H matrix first  H is sparsely populated with 1s  Fewer edges → less computations  Find the systematic H and G matrices  G will not be sparse

20. Soft Decision Decoding  Uses Tanner Graph representation with an iterative process  No “hard-clipping” of received code word  2dB performance gain over hard decision [2] 20

21. 21 High Level LDPC System Block Diagram

22. 22 Soft Decision Decoder Diagram

23. 23 -7.11158 -1.5320 -0.3289 5.7602 2.7111 0.4997 -5.1652 1.5357 -5.0942 1.2526 1 1 2 2 3 3 4 4 5 5 6 7 8 9 10

24. 24 -7.11158 -1.5320 -0.3289 5.7602 2.7111 0.4997 -5.1652 1.5357 -5.0942 1.2526 1 2 2 3 3 4 4 5 5 6 7 8 9 10 Re-Calculate Each Edge -1.5320 -0.3289 5.7602 1

25. 25 -7.11158 -1.5320 -0.3289 5.7602 2.7111 0.4997 -5.1652 1.5357 -5.0942 1.2526 1 2 2 3 3 4 4 5 5 6 7 8 9 10 Re-Calculate Each Edge -1.5320 -0.3289 5.7602 1

26. 26 -7.11158 -1.5320 -0.3289 5.7602 2.7111 0.4997 -5.1652 1.5357 -5.0942 1.2526 1 1 2 2 3 3 4 4 5 5 6 7 8 9 10 Re-Calculate Each Edge -1.5320 -0.3289 5.7602 SUM -1.5320 Update Algorithm

27. 27 -7.11158 -1.5320 -0.3289 5.7602 2.7111 0.4997 -5.1652 1.5357 -5.0942 1.2526 1 1 2 2 3 3 4 4 5 5 6 7 8 9 10 Re-Calculate Each Edge -1.5320 5.7602 SUM -0.3289 Update Algorithm -0.3289

28. 28 -7.11158 -1.5320 -0.3289 5.7602 2.7111 0.4997 -5.1652 1.5357 -5.0942 1.2526 1 1 2 2 3 3 4 4 5 5 6 7 8 9 10 Re-Calculate Each Edge -1.5320 -0.3289 5.7602 This Updated Value is Sent back to Variable Node 1 SUM 5.7602 Update Algorithm 0.2096

29. 29 -7.11158 -1.5320 -0.3289 5.7602 2.7111 0.4997 -5.1652 1.5357 -5.0942 1.2526 1 2 2 3 3 4 4 5 5 6 7 8 9 10 Re-Calculate Each Edge -0.3289 5.7602 -7.11158 1

30. 30 -7.11158 -1.5320 -0.3289 5.7602 2.7111 0.4997 -5.1652 1.5357 -5.0942 1.2526 1 2 2 3 3 4 4 5 5 6 7 8 9 10 Re-Calculate Each Edge 5.7602 -7.11158 -1.5320 1

31. 31 -7.11158 -1.5320 -0.3289 5.7602 2.7111 0.4997 -5.1652 1.5357 -5.0942 1.2526 2 2 3 3 4 4 5 5 6 7 8 9 10 Re-Calculate Each Edge -7.11158 -1.5320 -0.3289 1 1

32. Decoding Algorithm 32  Difficult to implement on a FPGA  Solutions:  Find an approximation  Construct lookup table  Phi function:

33. Lookup table Approach 33 Note: all inputs are >=0

34. Simulation Results 34

35. Simulink LDPC System 35

36. 36 Encoder Comparison

37. Encoder with Xilinx blocks 38

38. Co-Simulation Results

39. 39 Xilinx LDPC Decoder

40. 40 Decoder Control Logic

41. 41 Check Node Implementation

42. 42 Conclusion  MATLAB/Simulink simulation of LDPC system has been completed.  An efficient approximation of decoding algorithm has been developed for hardware implementation.  Xilinx System generator design for the decoder has been constructed.  Comparison and verification has not been completed for those results from MATLAB and Xilinx system generator.  FPGA implementation and a scaled up system may not be completed.

43. 43 References [1] Valenti, Matthew. Iterative Solutions Coded Modulation Library Theory of Operation. West Virginia University, 03 Oct. 2005. Web. 23 Oct. 2012.. [2] B. Sklar, Digital Communications, second edition: Fundamentals and Applications, Prentice-Hall, 2000. [3] Xilinx System Generator Manual, Xilinx Inc., 2011.

44. Questions? 44

45. Appendix 45

46. Matrix Manipulation  46

47. Reducing Decoding Complexity  Square_add function: y = max_star(L1,L2) - max_star(0, L1+L2);  MAX* function: if (L1==L2) y = L1; return; end; y = max(L1,L2) + log(1+exp(-abs(L1-L2))); end; 47

48. Reducing Decoding Complexity  This: y = max(L1,L2) + log(1+exp(-abs(L1-L2)));  Becomes Approximated MAX* function: x = -abs(L1-L2); if ((x =-2)) y = max(L1,L2) + 3/8; else y = max(L1,L2); end;  No costly log function 48

49. In Practice 49 Using MATLAB’s Code Profiler… MAX* function takes: 25.85s of simulation Approx. MAX* function takes: 28.02s of equally sized simulation Difference of 2.17s

50. Simulation Results 50  (10,5) Code  1000 codewords per datapoint, or  10,000 bits

51. Timeline 50

52. Division of Labor Zack  Simulink Model  Xilinx System generator design of decoder  Implementation of VHDL on FPGA  Performance analysis of FPGA implementation Matt  MATLAB Simulation  Error Performance Analysis  Xilinx System generator design of encoder  Performance analysis of MATLAB/Xilinx implementation 52