1. 1/2550A. Yaicharoen1 Programmable Logic Devices

2. 1/2550A. Yaicharoen2 General structure of PLDs

3. 1/2550A. Yaicharoen3 (a) Symbol (b) Logic equivalent Buffer/inverter

4. 1/2550A. Yaicharoen4 (a) Before programming (b) After programming Programming by Blowing Fuses

5. 1/2550A. Yaicharoen5 (a) Unprogrammed and-gate (b) Unprogrammed or-gate (c) Programmed and-gate realizing the term ac (d) Programmed or-gate realizing the term a + b (e) Special notation for an and-gate having all its input fuses intact (f) Special notiation for an or-gate having all its input fuses intact (g) And-gate with nonfusible inputs (h) Or-gate with nonfusible inputs PLD Notation

6. 1/2550A. Yaicharoen6 Types of PLDs Programmable ROM (PROM)  Fixed AND-array, programmable OR-array Programmable Logic Array (PLA)  Programmable AND-array and OR-array Programmable Array Logic (PAL)  Programmable AND-array, Fixed OR-array

7. 1/2550A. Yaicharoen7 Structure of a PROM

8. 1/2550A. Yaicharoen8 A 2 n  m PROM

9. 1/2550A. Yaicharoen9 Using a PROM for logic design

10. 1/2550A. Yaicharoen10 Logic diagram of an n  p  m PLA

11. 1/2550A. Yaicharoen11

12. 1/2550A. Yaicharoen12

13. 1/2550A. Yaicharoen13 Example of combinational logic design using a PLA. (a) Maps showing the multiple-output prime implicants. (b) Partial covering of the f 1 and f 2 maps. (c) Maps for the multiple-output minimal sum. (d) Realization using a 3  4  2 PLA. Example

14. 1/2550A. Yaicharoen14 (a) Circuit diagram. (b) Symbolic representation. Ex-Or-gate with a Programmable Fuse

15. 1/2550A. Yaicharoen15 General structure of a PLA having true and complemented output capability More on PLA

16. 1/2550A. Yaicharoen16 Karnaugh maps for the functions f 1 (x,y,z) =  m(1,2,3,7) and f 2 (x,y,z) =  m(0,1,2,6) Example

17. 1/2550A. Yaicharoen17 Two realizations of f 1 (x,y,z) =  m(1,2,3,7) and f 2 (x,y,z) =  m(0,1,2,6). (a) Realization based on f 1 and 2 (b) Realization based on 1 and 2 Example

18. 1/2550A. Yaicharoen18 A simple 4-input, 3-output PAL device