1. Xin-Wei Shih and Yao-Wen Chang

2.  Introduction  Problem formulation  Algorithms  Experimental results  Conclusions

3.  Skew-minimized buffered clock-tree synthesis plays an important role in high- performance VLSI designs for synchronous circuits.  Due to the insufficient accuracy of existing timing models for modern chip design, embedding simulation process into a clock- tree synthesis flow becomes inevitable.

4.  A possible way to improve the speed is performing the clock construction by structure optimization. ◦ Mesh  In this paper, a novel timing-model independent buffered clock tree synthesis method is proposed. ◦ Buffering and wiring structures of all paths from the clock source to its sinks are almost the same.

5.  Problem: Buffered Clock-Tree Synthesis (BCTS)  Instance: Given a set of clock sinks, a slew- rate constraint, and a library of buffers.  Question: Construct a buffered clock tree to minimize its skew, subject to no slew-rate violation.

7.  The number of leaves (sinks) can be treated as a multiplication sequence of branching. ◦ This multiplication sequence exactly forms a factorization.  Then, the BNP is arranged in the non- increasing order1 of the factorization list.

9.  A top-down manner like [10] or a bottom-up one like [7, 11], they can hardly apply to non binary tree structures.  Therefore, we propose a novel partitioning method, which can not only handle non- binary tree structures, but also achieve good quality in terms of the cluster diameter. ◦ cluster diameter : the maximum distance among sub-trees within the same cluster.

10.  We borrow the idea of cake cutting, i.e., slicing a cake into pieces from the center of the cake.

13.  Since the identical branch numbers at the same level are required in the symmetrical structure, a pseudo sink should be transformed into a dangling wire to maintain the symmetry.  For partitioning, we relax that the sizes of clusters in a partition can differ by at most one for the first recursion.  For node embedding, we let the embedding regions of pseudo sinks cover the entire chip.

14.  A top-down manner ◦ By tracing along the tree edges, once the slew rate is about to violate the constraint, identical buffers are inserted for all branches. ◦ Insert identical buffers in terms of the type and the size at the same level. ◦ The slew rate is approximated by accumulated capacitance starting from the latest inserted buffer.

16.  Implemented in the C++ programming language on a 2.6 GHz AMD-64 workstation.  Four ISPD’09 Clock Network Synthesis Contest benchmarks with no blockages [17] and the IBM benchmarks [19].  Use ngspice [13] simulation based on the 45nm process technology [14] to evaluate the quality.

17.  clock skew (skew)  clock-latency range(CLR)  total resource usage (usage)

20.  We have presented a fast timing-model independent buffered clock tree synthesis method to construct a symmetrical clock tree with little wiring overhead.  By symmetrically constructing a clock tree, the clock skew can be minimized without referring to simulation information.