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Overview Dynamic reconfiguration of FPGAs:

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Presentation on theme: "Overview Dynamic reconfiguration of FPGAs:"— Presentation transcript:

0 Brahim Al Farisi, Karel Bruneel, Dirk Stroobandt
StaticRoute: A novel router for the dynamic partial reconfiguration of FPGAs Brahim Al Farisi, Karel Bruneel, Dirk Stroobandt

1 Overview Dynamic reconfiguration of FPGAs:
Modular dynamic reconfiguration (MDR) Dynamic circuit specialization (DCS) Novel tool flow Experiments and results Conclusions Niet beginnen met lege slides. Volledige slide tonen. And then .. Vervangen door iets anders..

2 FPGA LUT FF 1 1 1 1 Configureerbaarheid FPGA gebruiken
1 1 1 Configureerbaarheid FPGA gebruiken Routing: switches controlled by bit values which are stored in memory cells.

3 Conventional FPGA tool flow
Input: textual description of functionality HDL design SYNTHESIS MAP PLACE ROUTE Configuration

4 Textual description: HDL design
in0 entity multiplexer is port( sel : in std_logic_vector(1 downto 0); in : in std_logic_vector(3 downto 0); out : out std_logic ); end multiplexer; architecture behavior of multiplexer is begin out <= in(conv_integer(sel)); end behavior; in1 out in2 in3 sel0 sel1

5 Conventional FPGA tool flow
Input: Textual description of functionality Output: FPGA configuration HDL design SYNTHESIS MAP 100101 011100 001111 PLACE ROUTE Configuration

6 Dynamic reconfiguration of FPGAs
Advantages: Smaller area Lower power usage Disadvantage: Reconfiguration time Goal: verminderen herconfiguratietijd Waarom Lower power en increased speed? Goal: area reduction with reduced reconfiguration time

7 Dynamic reconfiguration of FPGAs
2 tool flows: Modular Dynamic Reconfiguration (MDR) Dynamic Circuit Specialization (DCS) Goal: verminderen herconfiguratietijd Waarom Lower power en increased speed?

8 Modular Dynamic Reconfiguration (MDR)
Mode 1 Mode 2 SYNTHESIS SYNTHESIS MAP MAP PLACE PLACE ROUTE ROUTE Configuration 1 Configuration 2

9 MDR Different modes are implemented independently
Complete area is rewritten  Results in long reconfiguration times Evetnueel animatie toevoegen waarin area volledig herschreven wordt

10 Dynamic Circuit specialization
Design with parameters: input signals that only change once a while Implement dependency on parameters using dynamic reconfiguration Evetnueel animatie toevoegen waarin area volledig herschreven wordt

11 Dynamic circuit specialization
Input: annotated textual description of functionality Param. HDL SYNTHESIS TMAP TPLACE Toolflow volledig tonen van in het begin Misschien hiervoor dynamic circuit specialization in het algmeen uitleggen. TROUTE Param. Conf.

12 Parameterised HDL design
entity multiplexer is port( --BEGIN PARAM sel : in std_logic_vector(1 downto 0); --END PARAM in : in std_logic_vector(3 downto 0); out : out std_logic ); end multiplexer; architecture behavior of multiplexer is begin out <= in(conv_integer(sel)); end behavior; in0 in1 out in2 in3 sel0 sel1

13 Dynamic circuit specialization
Input: Annotated textual description of functionality Param. HDL SYNTHESIS TMAP TPLACE TROUTE Param. Conf.

14 Dynamic circuit specialization
Input: Annotated textual description of functionality Output: Parameterised configuration Param. HDL SYNTHESIS TMAP 1A0101 0111B0 0C1111 A = sel0 AND sel1 B = sel1 C = sel0 OR sel1 TPLACE TROUTE Param. Conf.

15 TRoute

16 Dynamic Circuit Specialization
Reduced reconfiguration time Takes as input 1 parameterised design How to implement several modes with DCS? Evetnueel animatie toevoegen waarin area niet volledig herschreven wordt

17 Goal of our research Develop tool flow for dynamic reconfiguration of multi-mode circuits Reduce reconfiguration time Combined routing of different modes using TRoute:  Increase correlation between configurations of the different modes

18 Novel tool flow Mode 1 Mode 2 SYNTHESIS SYNTHESIS MAP MAP PLACE PLACE
ROUTE Merge ROUTE Verwijzen naar wat ik al gezegd bij MDR Configuration 1 Configuration 2 TROUTE Param. Conf.

19 TRoute for multi-mode circuits

20 Experiments Regular expression matching hardware and general MCNC benchmarks Circuits of LBs 2 to 5 modes considered Comparison of MDR and DCS (this work) Metrics: Reconfiguration time Wire length (of each mode separately) Extra figuur voor draadlengte

21 Results – Reconfiguration time
Speed-up of routing reconfiguration time Speed-up of total reconfiguration time Extra figuur voor draadlengte

22 Results – Reconfiguration time routing (MDR)
Error bars uitleggen

23 Results – Reconfiguration time routing (DDR)
Results – Reconfiguration time routing (MDR) Error bars uitleggen

24 Results – Total reconfiguration time (MDR)
Error bars uitleggen

25 Results – Total reconfiguration time (DDR)
Error bars uitleggen

26 Results - Wire length Extra figuur voor draadlengte

27 Results – Wire length

28 Conclusions Using novel tool flow that uses TRoute:
Total reconfiguration speed-up of 3X to 5X Increase in wire length between 10 to 25 percent

29 Brahim Al Farisi, Elias Vansteenkiste, Karel Bruneel, Dirk Stroobandt
A novel tool flow for increased routing configuration similarity in multi-mode circuits Brahim Al Farisi, Elias Vansteenkiste, Karel Bruneel, Dirk Stroobandt

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