1. 1 Copyright © 2013 Elsevier Inc. All rights reserved. Chapter 1 Embedded Computing

2. 2 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.1 Major levels of abstraction in the design process.

3. 3 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.2 Sample requirements form.

4. 4 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.3 Block diagram for the moving map.

5. 5 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.4 Hardware and software architectures for the moving map.

6. 6 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.5 An object in UML notation.

7. 7 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.6 A class in UML notation.

8. 8 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.7 Derived classes as a form of generalization in UML.

9. 9 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.8 Multiple inheritance in UML.

10. 10 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.9 Links and associations.

11. 11 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.10 A state and transition in UML.

12. 12 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.11 Signal, call, and time-out events in UML.

13. 13 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.12 A state machine specification in UML.

14. 14 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.13 A sequence diagram in UML.

15. 15 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.14 A model train control system.

16. 16 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.15 Bit encoding in DCC.

17. 17 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.16 Class diagram for the train controller commands.

18. 18 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.17 UML collaboration diagram for major subsystems of the train controller system.

19. 19 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.18 A UML class diagram for the train controller showing the composition of the subsystems.

20. 20 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.19 Classes describing analog physical objects in the train control system.

21. 21 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.20 Controlling motor speed by pulse-width modulation.

22. 22 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.21 Class diagram for the panel and motor interface.

23. 23 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.22 Class diagram for the Transmitter and Receiver.

24. 24 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.23 Class diagram for the Formatter class.

25. 25 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.24 Sequence diagram for transmitting a control input.

26. 26 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.25 State diagram for the formatter operate behavior.

27. 27 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.26 State diagram for the panel-activate behavior.

28. 28 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.27 Class diagram for the Controller class.

29. 29 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.28 State diagram for the Controller operate behavior.

30. 30 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.29 Sequence diagram for a set-speed command received by the train.

31. 31 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 1.30 Refined class diagram for the train controller commands.

32. 32 Copyright © 2013 Elsevier Inc. All rights reserved. UN Figure1.1

33. 33 Copyright © 2013 Elsevier Inc. All rights reserved. UN Figure1.2