1. Saverio Minutoli INFN Genova 1 T1 Electronic status Electronic items involved: Anode Front End Card Cathode Front End Card Read-Out Control card Slow Control Ring T1 Trigger Architecture H.V. Distribution T1 mini DAQ Cern Collab. Meeting 12 Sept 2007

2. Saverio Minutoli INFN Genova 2 Ten different types (dimensions and connections). All schematics and layouts done. Ready for the mass production Production of some pcb types will start next week Preproduction of CSC-5P done.  Installed on two CSCs at GIF and H8. Static tests done Routing and VFAT Hybrid Mech. matching  Dynamic tests ( to be complete ): Compatibility with VFAT Preamp. stage Grounding and Shielding AFEC

3. Saverio Minutoli INFN Genova 3 CFEC (CMS chips) (1)  Manage 64 chs  The board has been completely debugged with a Digital Mezzanine developed by the Genoa group.  The results obtained are compliant with the requirements.  We have 8 cards fully equipped, enough to read-out 1.5 CSCs.  To be tested with the digital VFAT.  Minor pcb modifications for the mass production in progress.  New version will hosts the R.H. low voltages regulator.

4. Saverio Minutoli INFN Genova 4 CFEC (VFAT hybrid) (2) Manage 128 chs Static tests done Routing and VFAT Hybrid Mech. Matching  Dynamic tests (to be done): Compatibility with VFAT Preamp. stage. new CFEC layout following the AFEC rules. We have 10 cards fully equipped, enough to read-out 3 CSCs.  To be tested with the analog VFAT Hybrid.

5. Saverio Minutoli INFN Genova 5 ROC (1) The design is almost fixed. Need some confirmations from W.S. or G.A about parts of the circuit !!!!!! Layout within 1 month  board could be available middle/end of October. The ROC board manage two CSCs detectors. Collect the serial data streams coming out from the VFAT hybrids and transmit them to the Counting Room, via an optical link (1 GOH). Also the trigger bits are sent via optical links (2 GOHs). Hosts the Slow Control Ring node (CCUM), distribute to the FE electronic cards the I 2 C control line. Distribuite the power supply and the I 2 C lines to the new TOTEM DOHM. Control and generate the trigger bits logic transmission signal, and perform the trigger bits synchronization circuitry. Distribute and regenerate the Clock and T1 Fast Commands to all the FE boards. Hosts dedicate spy connectors for a mezzanine, in order to emulate the CCUM functions and acquire all the data and trigger bits coming out from the FE cards. The schematic is in progress, it inherits the skeleton of the T1 Digital Mezzanine design.

6. Saverio Minutoli INFN Genova 6 ROC (2) CSCnCSCn C S C n+1 TR_VFAT BC0 TR_MUX DAV CRT4T DAV_REDU NDANCY LVDS2 CMOS 1 3 8 10 DAVs 1/0

7. Saverio Minutoli INFN Genova 7 ROC (3) BC0b IDLEb/ON TR_GOH_DAV I/O CCUM MUX CSC1 A DATA_GOH_DAV I/O CCUM MUX I/O CCUM CSC2 A K K K TRIGGER DAV DATA DAV Has been tested (W.S.) ???

8. Saverio Minutoli INFN Genova 8 Slow Control Ring (1) Based on the new TOTEM DOHM design (G.A.) Distributes the 40MHz LHC clock and serial Fast Commands (labeled as T1). Each SCR node manage and distribute the I 2 C communications lines. The I 2 C is the only way through what we can modify the setting parameters of the major electronic devices (VFAT included) involved in the FE Totem project. According documentation the I 2 C limitations are: The maximum number of nodes (~11). The maximum cable length (50cm/branch, 2-3m in total).

9. Saverio Minutoli INFN Genova 9 Slow Control Ring (2) I 2 C – P.S. I2CI2C TOTEM DOHM ROCs ¼ T1

10. Saverio Minutoli INFN Genova 10 T1 Trigger Architecture (1) All the trigger bits generated by the T1 detector are sent to the Totem Trigger System via optical link. T1 detector modularity is ¼, this means 15 CSCs chambers. Each CSC generate 16 trigger bits  1 GOL. Globally ¼ T1 needs 15 fibers to be able to transfer all the trigger information. No spare GOL channels available. The trigger bits sent to the Counting Room, will be collected on the Trigger TOT-FED, that can manage 36 fibers, shared in three groups of 12 fibers each. We have 15 fibers per each ¼ T1. In order to merge and manipulate with a dedicate algorithm all the trigger bits, we will need a mezzanine (to be defined) to add to the Trigger TOT-FED. The trigger system is not completely fixed, need some more iterations within the trigger group.

11. Saverio Minutoli INFN Genova 11 T1 Trigger Architecture ~6k wires CSC ROC T1 ARM 8 1 x2 2 30 ~6k wires CSC ROC T1 ARM 8 1 x2 2 x15 30 T1 TRG_TOTFED 12 33 T1 TRG_TOTFED 12 33 GLOBAL TRG_TOTFED 8bits XX COUNTING ROOM CAVERN Trigger Bits 2 x 480 = 960 x15 x2 (Needs TRG algo.) LV1 Y (16bits) VFAT (16bits) 8bits VFAT

12. Saverio Minutoli INFN Genova 12

13. Saverio Minutoli INFN Genova 13 T1 mini DAQ back-up (1) In order to have a back-up solution for H8 and bld.188, we are setting up a small and portable DAQ system to read one VFAT hybrid. The system performs the I 2 C protocol functionalities. The slow commands are managed through a PC and a custom software. The implementation of the all VFAT commands is in progress. The system hosts a DCU device to read back the VFAT internal DACs registers. The VFAT serial data-out will be acquired by a FPGA that decodes the data and sends the information out to the PC via an USB port. The trigger bits are manipulated by the same FPGA. The system can generate the clock and T1 commands locally or remotely. The system is based on the T1 Digital Mezzanine. A possible extension of the system to read an entire chamber (using several T1 D.M. already available) is under evaluation. Most of the pieces are available (HW, FW), expected to be available within October.

14. Saverio Minutoli INFN Genova 14 T1 mini DAQ back-up (2)

15. Saverio Minutoli INFN Genova 15 VFAT  CSC compatibility verification AFEC ready CFEC (both types) need to be tested with CSC New designs can be ready within a month. ROC available middle/end October Mini DAQ ready within October H.V.(CAEN) and L.V.(WIENER) ready to be purchased Need to procure the CERN components: R.H. logic devices (lvds_mux, lvdsbuf, crt902, crt4t, crt245 …) GOH 7.3, etc…. CSCs test in progress to the H8 test beam Finally some inputs have been read with VFAT through the DAQ in H8 Small, but important results obtained. Conclusions