1. MonolithIC 3D Inc., Patents Pending MonolithIC 3D ICs RCAT approach 1 MonolithIC 3D Inc., Patents Pending

2. 3D ICs at a glance A 3D Integrated Circuit is a chip that has active electronic components stacked on one or more layers that are integrated both vertically and horizontally forming a single circuit. Manufacturing technologies: -Monolithic -TSV based stacking -Chip Stacking w/wire bonding MonolithIC 3D Inc, Patents Pending 2

3. MonolithIC 3D A technology breakthrough allows the fabrication of semiconductor devices with multiple thin tiers (<1um) of copper connected active devices utilizing conventional fab equipment. MonolithIC 3D Inc. offers solutions for logic, memory and electro- optic technologies, with significant benefits for cost, power and operating speed. MonolithIC 3D Inc., Patents Pending 3

4. Comparison of Through-Silicon Via (TSV) 3D Technology and Monolithic 3D Technology The semiconductor industry is actively pursuing 3D Integrated Circuits (3D-ICs) with Through-Silicon Via (TSV) technology (Figure 1). This can also be called a parallel 3D process. As shown in Figure 2, the International Technology Roadmap for Semiconductors (ITRS) projects TSV pitch remaining in the range of several microns, while on-chip interconnect pitch is in the range of 100nm. The TSV pitch will not reduce appreciably in the future due to bonder alignment limitations (0.5-1um) and stacked silicon layer thickness (6-10um). While the micron-ranged TSV pitches may provide enough vertical connections for stacking memory atop processors and memory-on-memory stacking, they may not be enough to significantly mitigate the well-known on- chip interconnect problems. Monolithic 3D-ICs offer through-silicon connections with <50nm diameter and therefore provide 10,000 times the areal density of TSV technology. MonolithIC 3D Inc., Patents Pending 4

5. MonolithIC 3D  Inc. Patents Pending 5 Typical TSV process  TSV diameter typically ~5um  Limited by alignment accuracy and silicon thickness Processed Top Wafer Processed Bottom Wafer Align and bond TSV Figure 1

6. Two Types of 3D Technology 6 3D-TSV Transistors made on separate wafers @ high temp., then thin + align + bond TSV pitch > 1um* Monolithic 3D Transistors made monolithically atop wiring (@ sub-400 o C for logic) TSV pitch ~ 50-100nm 10um- 50um 100 nm * [Reference: P. Franzon: Tutorial at IEEE 3D-IC Conference 2011]

7. Figure 2 ITRS Roadmap compared to monolithic 3D MonolithIC 3D Inc., Patents Pending 7

8. TSV (parallel) vs. Monolithic (sequential) MonolithIC 3D Inc., Patents Pending 8 Source: CEA Leti Semicon West 2012 presentationCEA Leti Semicon West 2012 presentation

9. The Monolithic 3D Challenge  Once copper or aluminum is added on for bottom layer interconnect, the process temperatures need to be limited to less than 400ºC !!!  Forming single crystal silicon require ~1,000ºC  Forming transistors in single crystal silicon require ~800ºC  The TSV solution overcame the temperature challenge by forming the second tier transistors on an independent wafer, then thinning and bonding it over the bottom wafer (‘parallel’) The limitations:  Wafer to wafer misalignment ~ 1µ  Overlaying wafer could not be thinned to less than 50µ

10. The Monolithic 3D Innovation  Utilize Ion-Cut (‘Smart-Cut’) to transfer a thin (<100nm) single crystal layer on top of the bottom (base) wafer  Form the cut at less than 400ºC *  Use co-implant  Use mechanical assisted cleaving  Form the bonding at less than 400ºC * * See details at: Low Temperature Cleaving, Low Temperature Wafer Direct BondingLow Temperature CleavingLow Temperature Wafer Direct Bonding  Split the transistor processing to two portions  High temperature process portion (ion implant and activation) to be done before the Ion-Cut  Low temperature (<400°C) process portion (etch and deposition) to be done after layer transfer See details in the following slides:

11. Monolithic 3D ICs Using SmartCut technology - the ion cutting process that Soitec uses to make SOI wafers for AMD and IBM (million of wafers had utilized the process over the last 20 years) - to stack up consecutive layers of active silicon (bond first and then cut). Soitec’s Smart Cut Patented* Flow:SmartCut Soitec’s Smart Cut Patented* Flow: MonolithIC 3D Inc., Patents Pending 11 *Soitec’s fundamental patent US 5,374,564 expired Sep. 15, 2012

12. Monolithic 3D ICs Ion cuttingIon cutting: the key idea is that if you implant a thin layer of H+ ions into a single crystal of silicon, the ions will weaken the bonds between the neighboring silicon atoms, creating a fracture plane (Figure 3). Judicious force will then precisely break the wafer at the plane of the H+ implant, allowing you to in effect peel off very thin layer. This technique is currently being used to produce the most advanced transistors (Fully Depleted SOI, UTBB transistors – Ultra Thin Body and BOX), forming monocrystalline silicon layers that are less than 10nm thick. MonolithIC 3D Inc., Patents Pending 12

13. Figure 3 Using ion-cutting to place a thin layer of monocrystalline silicon above a processed (transistors and metallization) base wafer MonolithIC 3D Inc., Patents Pending 13 p- Si Oxide p- Si Oxide H Top layer Bottom layer Oxide Hydrogen implant of top layer Flip top layer and bond to bottom layer Oxide p- Si Oxide H Cleave using <400 o C anneal or sideways mechanical force. CMP. Oxide Similar process (bulk-to-bulk) used for manufacturing all SOI wafers today p- Si

14. MonolithIC 3D – The RCAT path  The Recessed Channel Array Transistor (RCAT) fits very nicely into the hot-cold process flow partition  RCAT is the transistor used in commercial DRAM as its 3D channel overcomes the short channel effect  Used in DRAM production @ 90nm, 60nm, 50nm nodes  Higher capacitance, but less leakage, same drive current The following slides present the flow to process an RCAT without exceeding the 400ºC temperature limit MonolithIC 3D Inc., Patents Pending 14

15. RCAT – a monolithic process flow MonolithIC 3D Inc., Patents Pending 15 Wafer, ~700µm ~100nm P- N+ P- Using a new wafer, construct dopant regions in top ~100nm and activate at ~1000º C Oxide

16. MonolithIC 3D Inc. Patents Pending 16 ~100nm P- N+ P- Oxide Implant Hydrogen for Ion-Cut H+ Wafer, ~700µm

17. MonolithIC 3D Inc. Patents Pending 17 ~100nm P- N+ P- ~10nm H+ Oxide Hydrogen cleave plane for Ion-Cut formed in donor wafer Wafer, ~700µm

18. MonolithIC 3D Inc. Patents Pending 18 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer H+ Flip over and bond the donor wafer to the base (acceptor) wafer Base Wafer, ~700µm Donor Wafer, ~700µm

19. MonolithIC 3D Inc. Patents Pending 19 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer Perform Ion-Cut Cleave Base Wafer ~700µm

20. 20 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Complete Ion-Cut Base Wafer ~700µm

21. 21 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Etch Isolation regions as the first step to define RCAT transistors Base Wafer ~700µm

22. 22 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Fill isolation regions (STI-Shallow Trench Isolation) with Oxide, and CMP Base Wafer ~700µm

23. 23 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Etch RCAT Gate Regions Base Wafer ~700µm Gate region

24. 24 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Form Gate Oxide Base Wafer ~700µm

25. 25 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Form Gate Electrode Base Wafer ~700µm

26. 26 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Add Dielectric and CMP Base Wafer ~700µm

27. 27 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Etch Thru-Layer-Via and RCAT Transistor Contacts Base Wafer ~700µm

28. 28 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Fill in Copper Base Wafer ~700µm

29. 29 ~100nm N+ P- Oxide 1µ Top Portion of Base (acceptor) Wafer MonolithIC 3D Inc. Patents Pending Add more layers monolithically Base Wafer ~700µm Oxide ~100nm N+ P-