1. Impact of Nanotopography on STI CMP in Future Technologies D. Boning and B. Lee, MIT N. Poduje, ADE Corp. J. Valley, ADE Phase-Shift W. Baylies, Baytech Group

2. April 2002Boning et al., Nanotopography/STI CMP2 Outline Review: Nanotopography Interaction with CMP –Experiments demonstrate oxide thinning over nanotopography What impact does nanotopography have on STI as we scale from 130 nm to 100 nm and beyond? Approach: –Simulate CMP of STI stacks over nanotopography –Yield Problem #1: failure to clear oxide –Yield Problem #2: excessive nitride thinning Conclusions: –Nanotopography requirements can be based on STI yield impact –Can generate yield problem maps given a measured nanotopography map

3. April 2002Boning et al., Nanotopography/STI CMP3 Review: Nanotopography SSP wafer, Diameter Scan (Filtered Data) using NanoMapper TM WAFER HEIGHT (nm) 100 80 60 40 20 0 -20 -40 -60 -80 - 100 Nanotopography Length Nanometer height variations occurring on millimeter lateral length scales in virgin silicon wafers 100 nm -100 nm

4. April 2002Boning et al., Nanotopography/STI CMP4 Problem: Oxide Thickness Deviation (or Oxide Thinning) During CMP Actual Final Surface, after CMP removal Oxide Thickness Deviation Final oxide surface, assuming uniform CMP removal CMP Remaining Oxide Initial oxide surface after conformal deposition Silicon with initial nanotopography feature mm distances

5. April 2002Boning et al., Nanotopography/STI CMP5 Nanotopography & Oxide Thinning SSP Wafer Data @ 20mm EE NanoMapper nanotopography filtered wafer height map Acumap inverted oxide thickness with zero mean High / Thin Low / Thick

6. April 2002Boning et al., Nanotopography/STI CMP6 Impact of Nanotopography in STI CMP? Previous experiments on blanket oxide over nanotopography show oxide thinning in CMP But… STI processes involve CMP of a multilayer oxide/nitride/oxide stack Si Nitride Oxide Before CMPAfter CMP Excessive nitride removal Fail to clear oxide

7. April 2002Boning et al., Nanotopography/STI CMP7 Approach: Simulate Effect of Nanotopography on CMP of STI Stack oxide nitride silicon STI stack over nanotopography: pre-CMP STI stack over nanotopography: post-CMP “Ideal” result: Complete removal of oxide No removal of nitride

8. April 2002Boning et al., Nanotopography/STI CMP8 Simulation Details Start with measured nanotopography data – Epi single-side polished substrate; use 20 mm EE Simulate CMP of STI stack on blanket wafer –Perform 3D contact wear simulation – find local pressures based on bending of elastic pad around surface –Consider 130 nm technology node: 300 nm oxide / 100 nm nitride / 10 nm pad oxide –CMP process: Nominal pad stiffness: E = 147 MPa 5:1 oxide:nitride polish rate selectivity Consider Two Cases: –Problem #1: Failure to clear –Problem #2: Excessive nitride polish

9. April 2002Boning et al., Nanotopography/STI CMP9 Problem #1: Failure to Clear Oxide Polish time is determined by initial clearing (initial endpoint) plus overpolish time –Polish to initial clear: 84 seconds for this wafer/stack –Assume fixed overpolish time: 14 seconds Examine regions where oxide remains –These result in device failure oxide nitride silicon STI stack: pre-CMP Initial clearing or “Endpoint” is detected when top points begin to clear Failure to Clear Oxide Post-CMP with too little overpolish

10. April 2002Boning et al., Nanotopography/STI CMP10 Simulated Result: Oxide Clearing Map 3% of wafer does not clear Initial Nanotopography Blue indicates uncleared areas Note visual correlation with initial nanotopography “low spots” Å Initial Nanotopography

11. April 2002Boning et al., Nanotopography/STI CMP11 Problem #2: Excessive Nitride Loss Failure to clear - causes incomplete transistor formation –Alternative: Increase overpolish time to ensure complete clearing of oxide in all nanotopography valleys everywhere on wafer Nanotopography thus forces additional overpolish time! –In addition to overpolish due to wafer level or chip pattern effects Resulting problem: excessive nitride loss - causes transistor performance degradation oxide nitride silicon STI stack: pre-CMP Remaining nitride STI stack: post-CMP Nitride Thinning

12. April 2002Boning et al., Nanotopography/STI CMP12 Simulation Details Extend CMP over-polish time until oxide has just finished clearing everywhere Plots: –Initial nanotopography –Total amount removed (oxide and nitride) –Nitride thinning –Potential device failure points Assume a 20% nitride film thickness loss budget

13. April 2002Boning et al., Nanotopography/STI CMP13 Initial Nanotopography Total Amount Removed Å Å E= 147 MPa

14. April 2002Boning et al., Nanotopography/STI CMP14 Total Removed Zoom on Total Removed Initial Nanotopography

15. April 2002Boning et al., Nanotopography/STI CMP15 Thinning of Nitride Layer (Under Oxide) Nitride Thinning E= 147 MPa Å Å Initial Nanotopography

16. April 2002Boning et al., Nanotopography/STI CMP16 Nitride Thinning – Device Failure Map Red indicates excessive nitride thinning – greater than 20 nm (10%) budget 4.5% Area Failure Initial Nanotopography Å E= 147 MPa Initial NanotopographyPotential Failure Locations

17. April 2002Boning et al., Nanotopography/STI CMP17 Effects of Pad Stiffness The pad stiffness may affect the amount of nitride thinning –Stiffer pads result in more thinning in certain regions on the wafer –Less stiff pads result in less thinning Trend in STI CMP is toward stiffer pads in order to reduce within-die variation due to pattern densities –This trend may conflict with nanotopography!

18. April 2002Boning et al., Nanotopography/STI CMP18 Comparison: Nitride Thinning & Failure Areas Å Soft Pad E = 70 MPa Medium Pad E = 147 MPa Stiff Pad E = 200 MPa 0.4% Failure Areas 8.1%4.5%

19. April 2002Boning et al., Nanotopography/STI CMP19 Future Generations As technology scales, film thicknesses will also decrease Nitride thinning budget for STI processes will also decrease Examine 130 nm to 100 nm transition Conservative Scaling Assumption: –nitride film thickness shrinks to 90 nm (from 100 nm) –thinning budget of 20% or 18 nm (from 20 nm)

20. April 2002Boning et al., Nanotopography/STI CMP20 28.37% Excessive Nitride Thinning – Device Failure Comparison 100 nm (18 N thin ) Soft Pad 130 nm (20 nm N thin ) 8.1% 4.5% 0.4% 36.81% 34.75% Failure Area% Medium PadStiff Pad

21. April 2002Boning et al., Nanotopography/STI CMP21 Modified Nanotopography Requirement 0.2% Soft Pad 6.6%3.6% Medium PadStiff Pad Given nitride thinning spec (18 nm), how much must we scale nanotopography to achieve same % failure area? –Example: Scale nanotopography by 90%, adjust polish time Conjecture for future nanotopography requirements: –Need to scale nanotopography height at same rate as nitride thickness –May need to improve nanotopography height or spatial characteristics more aggressively if STI CMP moves to stiffer pads

22. April 2002Boning et al., Nanotopography/STI CMP22 Conclusions Nanotopography can interact with CMP to cause device yield concerns in the STI process Yield concerns can be predicted and yield impact maps produced from nanotopography maps: –Problem #1: failure to clear oxide –Problem #2: excessive nitride thinning Degree of impact depends on pad stiffness Future technology scaling will require –Continued tightening of nanotopography specs –Full wafer measurement and analysis of nanotopography Future work: STI stack simulation on patterned wafers with nanotopography

23. April 2002Boning et al., Nanotopography/STI CMP23 References 1.D. Boning, B. Lee, N. Poduje, J. Valley, and W. Baylies, “Modeling and Mapping of Nanotopography Interactions with CMP,” MRS Spring Meeting, April 2002. 2.B. Lee, D. S. Boning, W. Baylies, N. Poduje, P. Hester, Y. Xia, J. Valley, C. Koliopoulos, D. Hetherington, H. Sun, and M. Lacy, “Wafer Nanotopography Effects on CMP: Experimental Validation of Modeling Methods,” MRS Spring Meeting, April 2001. 3.D. Boning, B. Lee, W. Baylies, N. Poduje, P. Hester, J. Valley, C. Koliopoulos and D. Hetherington, “Characterization and Modeling of Nanotopography Effects on CMP,” International CMP Symposium 2000, Tokyo, Japan, Dec. 4, 2000. 4.R. Schmolke, R. Deters, P. Thieme, R. Pech, H. Schwenk, and G. Diakourakis, “On the Impact of Nanotopography of Silicon Wafers on Post-Chemical Mechanical Polished Oxide Layers,” J. Electrochem. Soc., vol. 149, no.4, pp. G257-G265, 2002. 5.B. Lee, T. Gan, D. S. Boning, P. Hester, N. Poduje, and W. Baylies, “Nanotopography Effects on Chemical Mechanical Polishing for Shallow Trench Isolation,” Advanced Semiconductor Manufacturing Conference, Sept. 2000. 6.O. G. Chekina and L. M. Keer, “Wear-Contact Problems and Modeling of Chemical Mechanical Polishing,” J. Electrochem. Soc., vol. 145, no. 6, pp. 2100-2106, June 1998. 7.T. Yoshida, “Three-Dimensional Chemical Mechanical Polishing Process Model by BEM,” Proc. ECS Conf., Oct. 1999.