1. The MAPS sensor (reminder) MAPS with integrated data sparsification
Recent developments on Monolithic Active Pixel Sensors (MAPS) for charged particle tracking.
Michael Deveaux on behalf of
IPHC Strasbourg, IKF Frankfurt/M
(Irradiations: F.M. Wagner, MEDAPP, FRM II reactor Munich)
Outline
The MAPS sensor (reminder)
MAPS with integrated data sparsification
MAPS with depleted sensors
R&D on 3D integrated electronics
A roadmap for MAPS for CBM
Summary and conclusion

2. The operation principle of MAPS
+3.3V
Reset
+3.3V
Output
SiO2
SiO2
SiO2
N++
N++ N+ P+ P- P+
M. Deveaux, 13th CBM Collaboration Meeting, 11 March 2009, GSI, Germany

3. How to build fast MAPS for the MVD: IPHC Strasbourg
On - chip zero suppression
Discriminators
Sensor
array
Bonding pads
+ output Amplis.
Expected time
resolution:
~10 µs (~100 kFrame/s)
Readout bus
Pixel column
SUZE-1
MIMOSA-16 and 22
M. Deveaux, 13th CBM Collaboration Meeting, 11 March 2009, GSI, Germany

4. MIMOSA-22, a fast and big chip
Test the MIMOSA-16 concept with higher surface
32 cols x 128 pixels => 128 cols x 576 pixels
17 different (improved) pixels designs:
New high gain / low noise pixels
Radiation hard pixels
Build smaller pixels
18.4 μm instead of 25 µm
Read-out time 100 μs ( 104 frames/s )
JTAG slow control
Programmable test DACs for disciminator tests
40 MHz digital data output
Tested with Fe-55 source and CERN 100 GeV/c pion beam
M. Deveaux, 13th CBM Collaboration Meeting, 11 March 2009, GSI, Germany

5. Test results of the new preaplifyers
Standard SB-Pixel design (Mimosa-16):
Successfully used since MIMOSA-4
No dead time
Noise: ~15e- with on-pixel CDS, else ~ 9e-
New in
MIMOSA-22
Noise:
10 < N < 14 e− ENC + 5 e− ENC Fix pattern noise (individual pixel offset)
Rad hard: 1e− ENC more than standard version
CCE :
3x3 pixels : 70 – 80 %
5x5 pixels : 80 – 90 %
M. Deveaux, 13th CBM Collaboration Meeting, 11 March 2009, GSI, Germany

6. Beam test results of MIMOSA-22
Detection efficiency
Fake hit rate
Discriminator Threshold
All pixels of interest show:
Detection efficiency: >99.8%
Fake hit rate: O(10-4 – 10-5)
Spatial resolution: ~3.5 µm (~ Pitch / 5)
M. Deveaux, 13th CBM Collaboration Meeting, 11 March 2009, GSI, Germany

7. How to build fast MAPS for the MVD
SUZE – 1 data
sparsification circuit
Sensor
array
Discriminators
On - chip zero suppression
Bonding pads
+ output Amplis.
Pixel column
Readout bus
SUZE-1
Chip with integrated Ø and output memories (no pixels)
Algorithm:
Step1: find up to 6 series of 4 neighbour pixels / raw in block of 64 cols.
Step2: Read-out all blocks, keep up to 9 series of 4 pixels.
Output memory:
4 x (512x16 bits) taken from AMS I.P. lib.
Surface:
3.9 × 3.6 mm²
Test result:
Works fine up to 115% clock frequency
Can handle up to 100 hits/frame at 104 frame/s
M. Deveaux, 13th CBM Collaboration Meeting, 11 March 2009, GSI, Germany

8. Next Step: MIMOSA-26 SUZE-1 Ø -suppression circuit MIMOSA-22 Sensor
Pixels + Ø-suppression
Expanded surface:
1152 cols x 576 pixels
21.2 x 10.6 mm²
18.6 µm pixel pitch
Expanded data sparsification circuit
18 blocks of 64 columns
Max. 9 clusters per row
Data rate: 80 Mbits/s
SUZE-1
Ø -suppression
circuit
MIMOSA-22 Sensor
MIMOSA-26
M. Deveaux, 13th CBM Collaboration Meeting, 11 March 2009, GSI, Germany

9. Digital Data – Sync – Clock : To Digital DAQ
Tests of MIMOSA-26
Analogue Data & Clock
To Analogue DAQ
JTAG Interface Board PC // Port   LVDS
A0 – A3
JTAG
From DAQ
A4 – A7
JTAG
CTRL
Start &
Speak
From
DAQ
Sync - Clock
Analogue – 8 x Out Auxiliary board
Mimosa 26 Proximity board
Digital Auxiliary board
Digital Data – Sync – Clock : To Digital DAQ
Analogue Test of MIMOSA-26
Digital Test of MIMOSA-26
Readout boards for MIMOSA-26
PCB development: W.Dulinski
Boards assembly & Bonding: M.Imhoff – O.Clausse – C.Wabnitz – L.Ankenmann
Coordination test boards: M.Specht
M. Deveaux, 13th CBM Collaboration Meeting, 11 March 2009, GSI, Germany

10. Client / Server : PXI Crate data server + Supervisor PC data client
The test setup
Mi26 emulation with pattern generator
2 outputs 80 MHz / 8 Mhz
~ 10 k bits / frame
Client / Server : PXI Crate data server + Supervisor PC data client
Supervisor
PC Windows
PXI DAQ
Digital acquistion board
CPU board & HD
Keyboard and monitor
Function
Acquisition board control
Data deserialisation
Data transfer via Ethernet ( Server )
Software / Language
Graphical user interface ( GUI )
Monitoring & Analyse
Data transfer via Ethernet ( Client )
GUI & NI Board driver  Labview
Deserialisation & Ethernet  C
GUI  C++ Builder Borland
Processing  C & C++
Ethernet
The Operator: Gilles Claus
Status:
Slow control: OK
Readout: OK
First hits seen
Concern: Hot pixels
M. Deveaux, 13th CBM Collaboration Meeting, 11 March 2009, GSI, Germany

11. Radiation hardness Chapter
M. Deveaux, 13th CBM Collaboration Meeting, 11 March 2009, GSI, Germany

12. Tolerance against non-ionising radiation
+3.3V
Output
+3.3V
GND
SiO2
SiO2
GND
SiO2
SiO2 N+
P++
P++
N++
P++
Bulk damage
M. Deveaux, 13th CBM Collaboration Meeting, 11 March 2009, GSI, Germany
Non-ionising radiation
Energy deposit into crystal lattice

13. Tolerance against non-ionising radiation
+3.3V
Output
+3.3V
GND
SiO2
SiO2
GND
SiO2
SiO2 N+
P++
P++
N++
P++
M. Deveaux, 13th CBM Collaboration Meeting, 11 March 2009, GSI, Germany

14. Tolerance against non-ionising radiation
+3.3V
Output
+3.3V
GND
SiO2
SiO2
GND
SiO2
SiO2 N+
P++
P++
N++
P++ E
M. Deveaux, 13th CBM Collaboration Meeting, 11 March 2009, GSI, Germany

15. The “impossible” chip: MIMOSA-25
MIMOSA-25 (XFAB 0.6µm PIN)
Partially depleted epitaxial layer
13k Pixels
Pixel pitch: 20, 30, 40µm
Only 3 metal layers
=> No onchip – CDS possible
Irradiated with up to 3x1013 neq/cm²
at the FRM – II Reactor Garching
(Forschungsneutronenquelle Heinz-Maier-Leibnitz)
Tests ongoing.
M. Deveaux, 13th CBM Collaboration Meeting, 11 March 2009, GSI, Germany

16. Landau MP (in electrons) versus cluster size
MIMOSA-25, first results
(Ru beta) 20 µm pitch, self-bias before and after neutron irradiation
Very promising. Beam test is needed to conclude.
Draw back: Process is NOT compatible with on-pixel CDS
Landau MP (in electrons) versus cluster size
Usual MIMOSA
(Beam test)
M. Deveaux, 13th CBM Collaboration Meeting, 11 March 2009, GSI, Germany

17. Opto electronics readout
Pixels for CBM Phase-2
On - chip zero suppression
Discriminators
Sensor
array
Bonding pads
+ output Amplis.
Integrating everything on one chip is always a compromise
How nice would it be:
Opto electronics readout
Special process
Noise !
Zero suppression
Small, fast transistors
CDS + Discriminators
Low noise transistors
Radhard Sensors
Low doping => Big transistors
M. Deveaux, 13th CBM Collaboration Meeting, 11 March 2009, GSI, Germany

18. 3D Integrated Circuits: introduction (Ray Yarema’s slides)
A 3D chip is generally referred to as a chip comprised of 2 or more layers of active semiconductor devices that have been thinned, bonded, and interconnected to form a “monolithic” circuit.
Often the layers (sometimes called tiers) are fabricated in different processes.
Industry is moving toward 3D to improve circuit performance. (Performance limited by interconnect)
Reduce R, L, C for higher speed
Reduce chip I/O pads
Provide increased functionality
Reduce interconnect power and crosstalk
HEP should watch industry and take advantage of the technology when applicable.
M. Deveaux, 13th CBM Collaboration Meeting, 11 March 2009, GSI, Germany

19. 3D Integrated Circuits: introduction (Ray Yarema’s slides)
There are 4 key technologies
Bonding between layers
Wafer thinning
Through wafer via formation and metallization
High precision alignment
Many of these technologies are also used in the development of SOI detectors
3D offers advantages over SOI detectors
Increased circuit density due to multiple tiers of electronics
Independent control of substrate materials for each of the tiers.
Ability to mate various
technologies in a monolithic
assembly
DEPFET + CMOS or SOI
CCD + CMOS or SOI
MAPS + CMOS or SOI
M. Deveaux, 13th CBM Collaboration Meeting, 11 March 2009, GSI, Germany

20. Processing steps 6µm chip + 7.5µm capton HgCdTe 0.25µm CMOS
R. Yarema, FNAL, Ziptronix
0.18µm CMOS
99.98% good pixels
M. Deveaux, 13th CBM Collaboration Meeting, 11 March 2009, GSI, Germany

21. R. Yarema, FNAL
M. Deveaux, 13th CBM Collaboration Meeting, 11 March 2009, GSI, Germany

22. MAPS for CBM – Phase 2
A consortium has been formed in order to use 3D Integrated Circuit
Design for building high performance pixels.
Players: Fermilab, IPHC, IRFU
M. Deveaux, 13th CBM Collaboration Meeting, 11 March 2009, GSI, Germany

23. 3D-VLSI run
Generate 2 tear chips by bonding two chips from the same wafer
Three tear chips are under development.
Long term development goal: 1014 neq/cm² + few µs integration time
First submission is planned spring 2009
M. Deveaux, 13th CBM Collaboration Meeting, 11 March 2009, GSI, Germany

24. MIMOSA roadmap for CBM (by Marc Winter)
MimoSIS-1:
2D-chip for SIS100 (D mesons in pA collisions)
Established AMS 0.35µm process
3 prototypes (2010,2011,2012) final prototyp by summer 2012
tInt < 40 µs, rad. tol. ~ 3 x 1012 neq/cm²
MimoSIS-2:
2D-chip for SIS300 (D meson in AA collisions)
Novel process with small feature size, stitching?
tInt < 30 µs, rad. tol. <1014neq/cm²
final prototyp by 2015
MimoSIS-3
3D-chip for SIS300, phase 2
tInt < 10 µs, rad. tol. ~1014neq/cm²
Development start by 2009
final prototyp > 2015 if 3D technology works
M. Deveaux, 13th CBM Collaboration Meeting, 11 March 2009, GSI, Germany

25. Summary
Fast chips:
MIMOSA-26 integrating the full discrimination chain was received from
production. First hits were seen.
Radiation hardness:
MIMOSA-25 is a first, partially depleted MAPS detector.
The chip is likely to show a radiation hardness >> 1013neq/cm²
(to be confirmed in beam tests).
Perspectives:
IPHC joined a consortium, which aims to study the use of 3D-VLSI
in pixel detector production.
If successful, this activity might provide us sensors with ~1014neq/cm²
and few microseconds in a long term perspective.
M. Deveaux, 13th CBM Collaboration Meeting, 11 March 2009, GSI, Germany