1. EE2174: Digital Logic and Lab Professor Shiyan Hu Department of Electrical and Computer Engineering Michigan Technological University CHAPTER 9 Sequential Circuits

2. 12-Sep-15 PJF - 2Chapter 9: Sequential Circuits Sequential Circuits Combinational Logic: Combinational Logic: Output depends only on current input Output depends only on current input Able to perform useful operations (add/subtract/multiply/…) Able to perform useful operations (add/subtract/multiply/…) Require cascading of many structures Require cascading of many structures Costly and inflexible Costly and inflexible

3. 12-Sep-15 PJF - 3Chapter 9: Sequential Circuits Sequential Circuits (cont.) Sequential Logic: Sequential Logic: Output depends not only on current input but also on past input values Output depends not only on current input but also on past input values Store information between operations (no need for cascading) Store information between operations (no need for cascading) Need some type of memory to remember the past input values Need some type of memory to remember the past input values

4. 12-Sep-15 PJF - 4Chapter 9: Sequential Circuits Sequential Circuits (cont.) Circuits that we have learned so far Information Storing Circuits Timed “States”

5. 12-Sep-15 PJF - 5Chapter 9: Sequential Circuits Sequential Logic: Concept Sequential Logic circuits remember past inputs and past circuit state. Sequential Logic circuits remember past inputs and past circuit state. Outputs from the system are “fed back” as new inputs (usually with delay). Outputs from the system are “fed back” as new inputs (usually with delay). The storage elements are circuits that are capable of storing binary information: memory. The storage elements are circuits that are capable of storing binary information: memory.

6. 12-Sep-15 PJF - 6Chapter 9: Sequential Circuits Synchronous vs. Asynchronous machines There are two types of sequential circuits: Synchronous (latch mode) sequential circuit: the behavior can be defined from knowledge of its signal at discrete instants of time. This type of circuits achieves synchronization by using a timing signal called the clock. Synchronous (latch mode) sequential circuit: the behavior can be defined from knowledge of its signal at discrete instants of time. This type of circuits achieves synchronization by using a timing signal called the clock. Asynchronous (fundamental mode) sequential circuit: the behavior is dependent on the order of input signal changes over continuous time, and output can change at any time (clockless). Asynchronous (fundamental mode) sequential circuit: the behavior is dependent on the order of input signal changes over continuous time, and output can change at any time (clockless).

7. 12-Sep-15 PJF - 7Chapter 9: Sequential Circuits Clock Signal Different duty cycles Clock generator: Periodic train of clock pulses

8. 12-Sep-15 PJF - 8Chapter 9: Sequential Circuits Synchronous Sequential Circuits: Flip flops as state memory The flip-flops receive their inputs from the combinational circuit and also from a clock signal with pulses at fixed intervals of time, as shown in the timing diagram. The flip-flops receive their inputs from the combinational circuit and also from a clock signal with pulses at fixed intervals of time, as shown in the timing diagram.

9. 12-Sep-15 PJF - 9Chapter 9: Sequential Circuits Buffers Inverters Storing Elements Can’t change the stored value!

10. 12-Sep-15 PJF - 10Chapter 9: Sequential Circuits S’R’ Latch (NAND version) S’ R’ Q Q’ 0 0 1 1 0 1 S’ R’ Q Q’ 0 1 1 0 1 0 Set 0 0 1 0 1 1 1 0 1 1 1 0 X Y NAND

11. 12-Sep-15 PJF - 11Chapter 9: Sequential Circuits S’R’ Latch (NAND version) S’ R’ Q Q’ 0 0 1 1 0 1 S’ R’ Q Q’ 1 1 1 0 1 0 Hold 0 0 1 0 1 1 1 0 1 1 1 0 X Y NAND 1 0 Set

12. 12-Sep-15 PJF - 12Chapter 9: Sequential Circuits S’R’ Latch (NAND version) S’ R’ Q Q’ 0 0 1 1 0 1 S’ R’ Q Q’ 1 0 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y NAND 1 0 Hold 1 0 Set 0 1 Reset

13. 12-Sep-15 PJF - 13Chapter 9: Sequential Circuits S’R’ Latch (NAND version) S’ R’ Q Q’ 0 0 1 1 0 1 S’ R’ Q Q’ 1 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y NAND 0 1 Hold 1 0 Set 0 1 Reset 1 0 Hold

14. 12-Sep-15 PJF - 14Chapter 9: Sequential Circuits S’R’ Latch (NAND version) S’ R’ Q Q’ 0 0 1 1 0 1 S’ R’ Q Q’ 0 0 1 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y NAND 0 1 Hold 1 0 Set 0 1 Reset 1 0 Hold 1 1 Disallowed

15. 12-Sep-15 PJF - 15Chapter 9: Sequential Circuits SR Latch with Clock signal Latch is sensitive to input changes ONLY when C=1

16. 12-Sep-15 PJF - 16Chapter 9: Sequential Circuits SR Latch with Clock signal (cont.) S’ R’ Q Q’ S R CLK S R CLK S’ R’ Q Q’ 0 0 1 1 1 Q 0 Q 0 ’ Store 0 1 1 1 0 0 1 Reset 1 0 1 0 1 1 0 Set 1 1 1 0 0 1 1 Disallowed X X 0 1 1 Q 0 Q 0 ’ Store

17. 12-Sep-15 PJF - 17Chapter 9: Sequential Circuits D Latch One way to eliminate the undesirable indeterminate state in the RS latch is to ensure that inputs S and R are never 1 simultaneously. This is done in the D latch: One way to eliminate the undesirable indeterminate state in the RS latch is to ensure that inputs S and R are never 1 simultaneously. This is done in the D latch:

18. 12-Sep-15 PJF - 18Chapter 9: Sequential Circuits D Latch (cont.) D S R CLK Q Q’ 0 0 1 Q 0 Q 0 ’ Store 0 1 1 0 1 Reset 1 0 1 1 0 Set 1 1 1 1 1 Disallowed X X 0 Q 0 Q 0 ’ Store 0 1 1 1 1 0 X 0 Q 0 Q 0 ’ D CLK Q Q’ S’ R’ Q Q’ S R CLK

19. 12-Sep-15 PJF - 19Chapter 9: Sequential Circuits D Latch with Transmission Gates C=1  TG1 closes and TG2 opens  Q’=D’ and Q=D C=1  TG1 closes and TG2 opens  Q’=D’ and Q=D C=0  TG1 opens and TG2 closes  Hold Q and Q’ C=0  TG1 opens and TG2 closes  Hold Q and Q’ 2 1

20. 12-Sep-15 PJF - 20Chapter 9: Sequential Circuits Flip-Flops Latches are “transparent” (= any change on the inputs is seen at the outputs immediately). Latches are “transparent” (= any change on the inputs is seen at the outputs immediately). This causes synchronization problems! This causes synchronization problems! Solution: use latches to create flip- flops that can respond (update) ONLY on SPECIFIC times (instead of ANY time). Solution: use latches to create flip- flops that can respond (update) ONLY on SPECIFIC times (instead of ANY time).

21. 12-Sep-15 PJF - 21Chapter 9: Sequential Circuits Alternatives in FF choice Type of FF Type of FF RS RS D JK JK Type of triggering Type of triggering Untriggered (asynchronous) Untriggered (asynchronous) Level-triggered (C=1) Level-triggered (C=1) Edge-triggered (rising or falling edge of C) Edge-triggered (rising or falling edge of C)

22. 12-Sep-15 PJF - 22Chapter 9: Sequential Circuits Master-Slave FF configuration using SR latches

23. 12-Sep-15 PJF - 23Chapter 9: Sequential Circuits S R CLK Q Q’ 0 0 1 Q 0 Q 0 ’ Hold 0 1 1 0 1 Reset 1 0 1 1 0 Set 1 1 1 1 1 Disallowed X X 0 Q 0 Q 0 ’ Hold Master-Slave FF configuration using SR latches (cont.) When C=1, master is enabled and stores new data, slave stores old data. When C=0, master’s state passes to enabled slave (Q=Y), master not sensitive to new data (disabled).

24. 12-Sep-15 PJF - 24Chapter 9: Sequential Circuits Master-Slave J-K Flip-Flop

25. 12-Sep-15 PJF - 25Chapter 9: Sequential Circuits Flip-Flop Problem The change in the flip-flop output is determined by the circuit frequency The change in the flip-flop output is determined by the circuit frequency S and/or R are permitted to change while C = 1 S and/or R are permitted to change while C = 1 Suppose that Q = 0 and S=1, R=0 -> S=0, R=0 Suppose that Q = 0 and S=1, R=0 -> S=0, R=0 The master latch sets to 1 The master latch sets to 1 A 1 is transferred to the slave A 1 is transferred to the slave Suppose that Q = 0 and S=1, R=0 -> S=0, R=0 -> S=0, R=1 -> S=0, R=0 Suppose that Q = 0 and S=1, R=0 -> S=0, R=0 -> S=0, R=1 -> S=0, R=0 The master latch sets and then resets The master latch sets and then resets A 0 is transferred to the slave A 0 is transferred to the slave

26. 12-Sep-15 PJF - 26Chapter 9: Sequential Circuits Flip-Flop Solution Use edge-triggering instead of master-slave Use edge-triggering instead of master-slave An edge-triggered flip-flop ignores the pulse while it is at a constant level and triggers only during a transition of the clock signal An edge-triggered flip-flop ignores the pulse while it is at a constant level and triggers only during a transition of the clock signal Edge-triggered flip-flops can be built directly at the electronic circuit level, or Edge-triggered flip-flops can be built directly at the electronic circuit level, or A master-slave D flip-flop which also exhibits edge- triggered behavior can be used. A master-slave D flip-flop which also exhibits edge- triggered behavior can be used.

27. 12-Sep-15 PJF - 27Chapter 9: Sequential Circuits Edge-triggered Flip-Flops Attach level-triggered D to level-triggered SR, using complemented clocks. Attach level-triggered D to level-triggered SR, using complemented clocks. D-Type Positive Edge-Triggered Flip-Flop:

28. 12-Sep-15 PJF - 28Chapter 9: Sequential Circuits Characteristic Tables Defines the logical properties of a flip- flop (such as a truth table does for a logic gate). Defines the logical properties of a flip- flop (such as a truth table does for a logic gate). Q(t) – present state at time t Q(t) – present state at time t Q(t+1) – next state at time t+1 Q(t+1) – next state at time t+1

29. 12-Sep-15 PJF - 29Chapter 9: Sequential Circuits Characteristic Tables (cont.) JK Flip-Flop JKQ(t+1)Operation 00Q(t) No change/Hold 010Reset 101Set 11Q(t)’Complement

30. 12-Sep-15 PJF - 30Chapter 9: Sequential Circuits Characteristic Tables (cont.) SR Flip-Flop SRQ(t+1)Operation 00Q(t) No change/Hold 010Reset 101Set 11?Undefined/Invalid

31. 12-Sep-15 PJF - 31Chapter 9: Sequential Circuits Characteristic Tables (cont.) D Flip-Flop DQ(t+1)Operation 00Set 11Reset Characteristic Equation: Q(t+1) = D(t)

32. 12-Sep-15 PJF - 32Chapter 9: Sequential Circuits Characteristic Tables (cont.) T Flip-Flop TQ(t+1)Operation 0Q(t)Hold 1Q(t)’Complement Obtained by JK Flip-Flop with J=K=T Characteristic Equation: Q(t+1) = T’Q(t) + TQ(t)’