1. 1 Catalog of useful (structural) modules and architectures In this course we will be working mostly at the BEHAVIORAL and STRUCTURAL levels. We will rely on the Altera design tools to do MOST of the physical design and optimization. Here we will quickly review the basic STRUCTURAL building blocks commonly used- -complete sets, muxes, demuxes, adders, flip- flops, counters, registers, memory, I/O. We will also briefly review the structure of typical basic computer architectures.

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11. 11 half- adder

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13. 13 full adder full adder full adder

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21. 21 Floating point arithmetic. A floating point number is usually represented by 3 parts: 1.Sign (+ or -, 1 bit) 2.Exponent (usually an integer, in “excess” notation) 3.Mantissa or significand (usually a fraction) So, for two positive numbers, we have: Addition /Subtraction: a.Adjust exponents so the numbers are the same size b.Add / Subtract significands; update sign c.Readjust exponent of answer if necessary Multiplication/division: a.Add/Subtract exponents; Multiply/Divide significands b.Adjust exponent of answer if necessary Basic operations can be done with integer modules, shifting. Special cases (e.g., overflow, underflow) cannot be ignored.

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24. 24 D Q CLK Q’

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26. 26 J Q CLK Q' K

27. 27 T Q CLK Q’ T (toggle) flip-flop. If T = 0, output is unchanged. If T = 1, output “toggles” or switches state. Can be implemented with a J- K flip-flop.

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31. 31 Control units. In a computer control unit the "state" of the unit determines what actions will be taken at a given time t. The "state" can be stored, for example, in a set of D flip-flops. If a unit has 2 n states, it can be represented in anywhere from n to 2 n flip=flops. If we use 2 n flip-flops, we call this a "one-hot" representation. Example: basic instruction execution sequence (how many states are required?): Fetch instruction: PC  MAR; MEM(MAR)  MDR; MDR  IR Decode instruction: decide on actions to be taken (e.g., jump, mem fetch / store) Fetch data: immediate operand (in instruction); register operand; memory operand (requires memory access); indirect address (requires 2 memory accesses); … Execute instruction: ALU operation; jump; subroutine call; interrupt; … Store result: immediate operand (in instruction); register operand; memory operand (requires memory access); indirect address (requires 2 memory accesses); …

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35. 35 Basic architectures: finite state machines, stack machines, Turing machines common parallel and distributed models

36. 36 1. Finite State Machine (FSM) 2. Stack Machine 3. Turing Machine / “Random Access Machine”/ Sequential Computer 4. Multiprocessor Machines

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38. 38 IN A CLOCK C B RESET Output: may be from each state (“Moore”) or from current state + input (“Mealey”)

39. 39 Control (fsm) “Top” Stack Popped Item (from “Top”) Combinational Logic I/O

40. 40 (Actual “RAM” Hierarchy) Registers Cache Main Memory (RAM) (Virtual Storage) {Hard Disk, Secondary Devices}

41. 41 4. Multiprocessor Machines: combinations of the above machines may work together to provide more powerful processing. Examples: Control Turing Machine ALU+RAM Vector Machine (“SIMD”) (ex. application:differential equations) Turing Machine Turing Machine Turing Machine Net- Worked or Distri- buted Processors (“MIMD”) (ex. applica- tion: databases) Turing Machine Turing Machine Turing Machine Turing Machine Pipelined Processors (“MISD”) (ex. application: signal processing) Printer Graphics Sound Typical PC CPU

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